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Trying to understand how a core is organized?

post #1 of 10
Thread Starter 
Hi, I am trying to get a further understanding in CPUs.

Recently, I read this article about HyperThreading (http://www.anandtech.com/show/868) and I understood it entirely. What it made me think about though is that: Why does this article supposedly say that a single-core Pentium 4 have two integer units and a single floating point unit?

Now, for as long as I've ever known, a single core, in terms of execution units, has had a single FPU and a single integer unit per core, along with it's cache and all that.

Though this article says that there are "7" execution units, and it refers to a single FPU and two integer units (which is 3?)

So I have a few questions regarding this:

First, do all modern CPUs have more than a single integer unit and a single FPU unit per core? This would exclude processors under the Bulldozer or Piledriver architecture as I know that those have two integer units and one FPU, such as this setup.

Second, what are these "7" execution units that the article refers to?

Third, if most modern CPUs (aside from FX modules) have a single integer unit and a single FPU per core, does that mean that the Pentium 4 referred to in the article has a setup similar to the modern FX module?

Fourth, if most modern CPUs do NOT have a single integer unit and single FPU per core, how can we tell what CPU has what?

Thank you in advance for any answers!
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post #2 of 10
See, particularly pg 10: http://www.realworldtech.com/sandy-bridge/
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post #3 of 10
Thread Starter 
Quote:
Originally Posted by OS-Wiz View Post

See, particularly pg 10: http://www.realworldtech.com/sandy-bridge/

Gonna be honest here; a lot of page 10 went right over my head... I don't understand a lot of things that are going on there (I'll definitely save the material for later when I do understand though) and my questions are still unanswered (not through your fault, but through my lack of understanding)... doh.gif
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post #4 of 10
Well, the reason a core might have two AUs and just one FPU is that floating point opcodes simply don't occur that often vs simple arithmetic/integer opcodes.
Most modern microprocessors are pipelined, meaning opcodes are broken down into several chunks and as they pass thru the pipeline two or more chunks might be able to be executed in parallel.
To get you up to date on the basics, here's a good intro:http://en.wikipedia.org/wiki/X86
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post #5 of 10
Thread Starter 
Quote:
Originally Posted by OS-Wiz View Post

Well, the reason a core might have two AUs and just one FPU is that floating point opcodes simply don't occur that often vs simple arithmetic/integer opcodes.
Most modern microprocessors are pipelined, meaning opcodes are broken down into several chunks and as they pass thru the pipeline two or more chunks might be able to be executed in parallel.
To get you up to date on the basics, here's a good intro:http://en.wikipedia.org/wiki/X86

Ah yes, I understand pipelining and x86 basics; that much I have down.

What I don't understand is that in the article I posted, it stated that the P4 had two integer units and one FPU.

While I understand that this is possible and why they would do this; would this situation occur in say... An i5-3570k, where the processor does NOT have HT?

Also, do all CPUs with HT have an extra integer unit like the P4 mentioned in the article, or does HT simply allow the FPU to be used at the same time as the integer unit?
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post #6 of 10
The 7 execution units mentioned in the article left out a few others, e.g. hardware interrupt handler, clock interrupt handler, I/O handler, etc.
The number of AUs and FPUs is up to the implementer and may be shared across all cores and Hyper-threads or dedicated by core.
You'll have to find the i5-3570k's architecture design doc to see how they are implemented on that chip, if even available -- might be proprietary.
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post #7 of 10
Thread Starter 
Quote:
Originally Posted by OS-Wiz View Post

The 7 execution units mentioned in the article left out a few others, e.g. hardware interrupt handler, clock interrupt handler, I/O handler, etc.
The number of AUs and FPUs is up to the implementer and may be shared across all cores and Hyper-threads or dedicated by core.
You'll have to find the i5-3570k's architecture design doc to see how they are implemented on that chip, if even available -- might be proprietary.

I'm not exactly trying to gain knowledge on particular chips, but moreso chips in general.

So it seems that the numbers of integer units and FPUs have zero corelation to the number of cores?
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post #8 of 10
Core organization changes with architecture. It keeps improving the performance..
post #9 of 10
Thread Starter 
Quote:
Originally Posted by d6bmg View Post

Core organization changes with architecture. It keeps improving the performance..

But that still doesnt exactly answer my questions :/
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post #10 of 10
Quote:
Originally Posted by elemein View Post

So it seems that the numbers of integer units and FPUs have zero corelation to the number of cores?
No, each core must have access to at least one of each execution unit, e.g. AU, FPU, HW interrupt, etc. How that is done is up to the implementer.
EDIT: Actually only the control core/processor in a multi-core CPU needs access to the HW interrupt handler, clock interrupt, I/O handler, etc.
Again, read the article I mentioned earlier to get a good handle on CPU microprocessor architecture: http://api.viglink.com/api/click?format=go&key=7777bc3c17029328d03146e0ed767841&loc=http%3A%2F%2Fwww.overclock.net%2Ft%2F1373600%2Ftrying-to-understand-how-a-core-is-organized%23post_19584252&v=1&libid=1364076397037&out=http%3A%2F%2Fwww.realworldtech.com%2Fsandy-bridge%2F&title=Trying%20to%20understand%20how%20a%20core%20is%20organized%3F&txt=http%3A%2F%2Fwww.realworldtech.com%2Fsandy-bridge%2F&jsonp=vglnk_jsonp_13640766230022
Edited by OS-Wiz - 3/23/13 at 3:10pm
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