Paul, just to correct a few mini errors that you have made within your post.
Core has a 4 stage execution core (decoders), which Netburst (and K8) have 3. This allows Core to complete all 4 stages of processing in 1 cycle.
Core has a new and more advanced FPU (floating point unit). This is why the Core has extremely fast SuperPI and computational scores.
Core has a new, unified cache system. Whereas in Netburst the L2 Cache is seperated (2x2Mb L2), Core uses a fast unified Core (4MB)
First Core 2 Duo has indeed got a four stage array execution core processing unit. However this processing system is not a decoder. The only major decoder within the Core 2 Duo design is the x86 decoding system, which is different from the Execution Core.
The x86 decoding system (1 Complex + 3 Simple) decodes x86 instructions so the processor can processor them. The rate of this depends upon the complexity of the instruction.
For example if we had:
EAX - B1 + A1 = C1
This would be assigned as a simple instruction and therefore can be executed and processed within a single execution pass.
Secondly, regardless of the number of execution units within an x86 architecture processor, the execution rate will usually be less than that specified. For Core 2 Duo an execution rate of four will be hard to obtain given the complexity of current instructions. Therefore I would vote for a rate of two to three hypothetically.
The Floating Point Unit is not technically new. The FPU is made out of multiple units for execution and processing. The "new"FPU incorporates an additional unit, brining the FPU count to four units instead of three. Additional performance enhancements have also been added.
The cache is technically not unified, unified means that an item can do anything in computation terms. The cache is itself a shared system that can be addressed by a dual cache allocation system within both cores of the processors.
By creating a unified cache we would technically have had to allow standard file data to be stored within the Levels of Internal cache, this can not be done technically. Therefore the cache is not unified. Another point about this is that the cache can only address a singular form of data a pass, unification means that multiple data can simultaneously addressed of different types. This is not so, therefore unification is irrelevant in this case of the Core 2 Duo.