I seriously hope this is true.
However, I wouldn't be surprised if it isn't. 30% is a lot and I don't think the main purpose of steamroller was to increase IPC a lot, but rather increase parallel processing. Either way, I really really wish this is true.
One of the reasons why dual-core Bulldozer modules [the same may be said about Piledriver] are not completely efficient is because they have only one instruction decoder for two ALUs and one FPU. With steamroller, AMD not only incorporated two decoders per module, but also increased instruction cache size (to lower i-cache misses by 30%), enhanced instruction pre-fetch (the number of mis-predicted branches is down by 20% compared to Bulldozer ) as well as improved max-width dispatches per thread by 25%.
Is it just me or are they slowly going back to fully fledged cores ?Edited by MoGTy - 3/31/13 at 2:31pm