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[xbitlabs] AMD: We Are On Track With Steamroller Micro-Architecture in 2013.  

post #1 of 718
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amd_opteron_plans_roadmap_steamroller.jpg&width=550&height=276&cache=1&quality=88&aspect=0&format=
amd_steamroller_1.jpg&width=550&height=314&cache=1&quality=88&aspect=0&format=jpg
Quote:
Advanced Micro Devices has released a presentation for investors that puts the launch of the new Steamroller micro-architecture in 2013. While the company did not unveil what chips will feature Steamroller high-performance x86 cores this year, it implied that the new generation of server-class Opteron chips will be based on Steamroller, the micro-architecture AMD puts a lot of hopes on.

Source
post #2 of 718
This is good news.
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post #3 of 718
more performance per watt and higher IPC? Sounds nice, but when in 2013? I just wish AMD managed to release it at or near Haswell's release date to give buyers a second option.
post #4 of 718
Quote:
Originally Posted by ZealotKi11er View Post

This is good news.

I agree. This is what AMD needs to get back in the CPU game

The main problem was Bulldozer stuff wasn't geared toward real world and the scheduler in Zambezi had issues
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post #5 of 718
30% more IPC performance. WOW.

Does this mean it will be on par with Intel 3770k IPC?
    
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post #6 of 718
I've already seen those pictures with 30% ipc proposed increase, AMD gotta get back in the game.
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post #7 of 718
How will it compare to Ivy in terms of IPC
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post #8 of 718
I seriously hope this is true.

However, I wouldn't be surprised if it isn't. 30% is a lot and I don't think the main purpose of steamroller was to increase IPC a lot, but rather increase parallel processing. Either way, I really really wish this is true.

2cents.gif

EDIT :
Quote:
One of the reasons why dual-core Bulldozer modules [the same may be said about Piledriver] are not completely efficient is because they have only one instruction decoder for two ALUs and one FPU. With steamroller, AMD not only incorporated two decoders per module, but also increased instruction cache size (to lower i-cache misses by 30%), enhanced instruction pre-fetch (the number of mis-predicted branches is down by 20% compared to Bulldozer ) as well as improved max-width dispatches per thread by 25%.

Is it just me or are they slowly going back to fully fledged cores ?
Edited by MoGTy - 3/31/13 at 2:31pm
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post #9 of 718
More ipc through architecture improvements and a bump in clock speeds surely...I'm really interested in seeing how this will shape up.
Hopefully they don't take too long to launch like the first FX chips did, and won't disappoint like them. thumb.gif
post #10 of 718
Whenever I look at how they say (This and this has been improved) All I see in my eyes is FX Release disappointment.
I really hope they fixed there
this time.
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Overclock.net › Forums › Industry News › Hardware News › [xbitlabs] AMD: We Are On Track With Steamroller Micro-Architecture in 2013.