Ah, so by "certain transistors have been moved around" are you saying that Intel did a relayout of the die and moved some of the logic engines (or blocks) to reduce some latencys (and increase others) and the results is better floating point math in Xeons, but slower SSE operations (or whatever causes the slower Direct3D)?
The re-development of the design structure was not related to the changing of logic circuitry, MOSFETS and internal processing units.
I believe an additional Bipolar Junction Transistor was added, along with an enhanced categorical sub array for one of the Floating Point Units (I believe it was the multiply unit).
A singular instruction was apparently switched between the MMX instruction set, and the newly implemented Supplemental SSE3+ instruction set. The change in these instruction sets will allow both processors to obtain slightly better results at their proposed strengths. The strengths of this change can be detected in the "long run" more dramatically.