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AMD, IBM Talk Immersion, Low-K at 45nm

post #1 of 5
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Quote:
As part of the companies' ongoing R&D collaboration, IBM and AMD today presented papers at IEDM describing the use of immersion lithography, ultra-low-K interconnect dielectrics, and multiple enhanced transistor strain techniques for application to the 45nm microprocessor process generation.

AMD and IBM said they expect the first 45nm products using immersion lithography and ultra-low-K interconnect dielectrics to be available in mid-2008.

Current process technology uses conventional lithography, which, the companies said, has significant limitations in defining microprocessor designs beyond the 65nm process technology generation. Immersion lithography uses a transparent liquid to fill the space between the projection lens of the step-and-repeat lithography system and the wafer that contains hundreds of microprocessors. This provides increased depth of focus and improved image fidelity that can improve chip-level performance and manufacturing efficiency, the companies said. According to IBM and AMD, performance of an SRAM cell shows improvements of approximately 15 percent due to this enhanced process capability, without resorting to more costly double-exposure techniques.

In addition, the use of porous, ultra-low-K dielectrics to reduce interconnect capacitance and wiring delay further improves microprocessor performance and lowers power dissipation, the companies said. This advance is enabled through the development of an ultra-low-K process integration that reduces the dielectric constant of the interconnect dielectric while maintaining the mechanical strength. The addition of ultra-low-K interconnect provides a 15 percent reduction in wiring-related delay as compared to conventional low-K dielectrics, according to the duo.

The continued enhancement of AMD and IBM's transistor strain techniques, the companies said, has enabled the continued scaling of transistor performance while overcoming geometry-related scaling issues associated with migrating to 45nm process technologies. In spite of the increased packing density of the 45nm generation transistors, IBM and AMD said they have demonstrated an 80 percent increase in p-channel transistor drive current and a 24 percent increase in n-channel transistor drive current compared to unstrained transistors.

IBM and AMD, which have been collaborating on the development of next-generation semiconductor manufacturing technologies since January 2003, are not without competition. Texas Instruments has also expressed plans for immersion lithography at the 45nm node.

Looking out beyond today’s news, AMD and IBM are looking forward to a future of working on even smaller nodes. In November 2005, the two companies announced an extension of their joint development efforts until 2011 covering 32nm and 22nm process technology generations.
http://www.edn.com/index.asp?layout=...096&ref=nbednn

    
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post #2 of 5
Great find, as always boredom. Where do you find this stuff?

Hopefully they will stick to their schedule and deliver by 2008.
    
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post #3 of 5
Ahh... good 'ol AMD and IBM working to make the world a better place. I hope by 2012 we have 22nm chips... imagine how efficient they will/could be.
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post #4 of 5
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Originally Posted by Dockery View Post
Ahh... good 'ol AMD and IBM working to make the world a better place. I hope by 2012 we have 22nm chips... imagine how efficient they will/could be.
I doubt we'll be seeing 22nm for a while. It's getting harder and harder to develop smaller processes. Wonder what happens when we finally do get to 22nm... Can we possibly develop smaller processes? Or will the computer hardware industry come to a grinding halt? Doomsday maybe even?
    
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post #5 of 5
3D, or multigate transistors will be the next step. they will have the theoretical ability to cut power consumption in half.

Quote:
Infineon believes that 3D transistors can reduce leakage current dramatically. In today's press release, the company claims that the 3000-transistor test chip showed 10 times less leakage current than a single-transistor device. That factor will increase "significantly" in "32 nm devices and beyond," the firm stated. This effect alone could double the battery life of portable devices, according to Infineon.

Because the technology enables to build transistors "three-dimensionally" - as opposed to the planar transistors in production today - the space required to integrate a certain amount of transistors shrinks. According to Infineon, 65 nm multi-gate transistor architecture requires about 30% less two-dimensional space than single-gate technology with the same functions and performance.

Infineon's multi-gate transistors are still deep in their research phase and will not be used in mass-production until 2012 or later, Infineon said. Looking at today's semiconductor roadmaps, 32 nm and 22 nm semiconductor structures will be business as usual until then.
Linky

Let us not forget other new types of processors in development.
    
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