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1T/2T timing question

post #1 of 9
Thread Starter 
I noticed an option in the Asus A8N32-sli-deluxe bios 1303 for the 1T/2T timing.
What should I set it to? Also what does it do?
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post #2 of 9
well basically commands are either driven for one clock or 2 clocks, i think 2 is recommended for unbuffered dimms. And there is a text book explination.
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post #3 of 9
It is generaly assumed that 1T offers better performance at the cost of stability, while 2T is almost a must for anybody running more than 2 sticks of memory if they wish to stabley overclock.

If you are running 2x1gb, you can probably set it to 1T and help out benchmark scores a little, but if you start having stability issues, put it back at 2T.

Note: Don't expect miracles from 1T, most people only get a few miliseconds off thier SuperPI time.
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post #4 of 9
Quote:
Originally Posted by Chipp View Post
Note: Don't expect miracles from 1T, most people only get a few miliseconds off thier SuperPI time.
Contrary to popular belief, the Command rate or Command Per Clock rate is NOT a memory timing.

The CPU and most types of memory have an 8 byte data transfer bus. They transfer 8 bytes of data once, twice, or four times per clock tick. However, for efficiency the basic unit of data transfer is a 32 byte "burst" of data around the address of the data the CPU needs. Any CPU reference to memory is rounded up to a complete 32 byte block. This block is transferred in a burst of 4 consecutive 8 byte transfers. Your timing settings effect this transfer, not the Command per clock.

The Command Per Clock sets the Command Rate for the memory controller. At 1T, the controller can issue commands on every clock cycle, if set to 2T the controller can only issue commands only on every other bus cycle. With DDR, the 2T command rate had some poor transferrals since there was little use for the bus interleaving (Dual Channel Mode). Let us say that if you ran at a 2.5 - 3 - 3 latency then the read command would be issued 2 cycles after an bank activate command. This would negate 1T vs 2T correct? Since the issuance was held to 2 cycles there would be no need for a single cycle command rate.

But we have DDR running in Dual Channel Mode and this mode allows for an opening of more than one page in different banks of the same memory device (slots related to dual channel ie. Bank 1 and Bank 3, etc.). So the second bank activate command that follows after the first bank activate command can not be issued since a read command for the first bank has already been scheduled. This is considered a "Bus Contention" and because of it, the next available time slot for the next bank activate command would collide with the second read command for the possibility of a page hit. This would continue until there is a no-op (no operation) return. When there is a no-op return or interval then another bank activate command can be initiated. Because of this issue, dual channel is largely useless, not only is it useless but it can even slow bank activation. This issue follows with DDR2 but one of the reasons for the creation of the DDR2 standard was to eliminate this previously mentioned bus contention. The DDR2 standard created the Posted CAS characteristic, so that there was no need to wait for the Trcd function to be completed. The Posted CAS feature allowed for the Read command to be issued immediately after the bank activate command. But this "Feature" can only be useful with a 1T command rate since a 2T command rate would eliminate the use of this characteristic.

Thus in a DDR2 system, with dual channel bank interleaving enabled there will be a more responsive system. Now there are added latancy issues with DDR2 vs DDR1 so for this benefit to be more effectively seen, one needs very low latency DDR2 DRAM.

When one compares DDR at 3 - 4 - 4 - 8 and DDR2 at 3 - 4 - 4 - 8 (Both Dual channel, bank interleaved) there becomes no doubt that the DDR2 is a far better memory transaction at 1T vs 2T and the difference at the DDR level is far less pronounced.

So, don't expect miracles with DDR and 1T but with (high quality and low timing) DDR2 you can expect a far greater response from 1T vs 2T.

R
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post #5 of 9
Quote:
Originally Posted by Ropey View Post
Contrary to popular belief, the Command rate or Command Per Clock rate is NOT a memory timing.

So, don't expect miracles with DDR and 1T but with (high quality and low timing) DDR2 you can expect a far greater response from 1T vs 2T.

R
The CPC is misunderstood by most and as Ropey said... and myself many times in the past The CPCs timing is RAM to MB relative and not a timing effect of teh RAM itself.

Well written reply there Ropey

Also, in real world apps the loss equates to aprox. 3-5% with a 2T CPC setting, where as benchmarks erroneously greatly exaggerate the difference. Can I prove that, not actually but my source was very reliable
    
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post #6 of 9
Quote:
Originally Posted by Ropey View Post
Contrary to popular belief, the Command rate or Command Per Clock rate is NOT a memory timing.

The CPU and most types of memory have an 8 byte data transfer bus. They transfer 8 bytes of data once, twice, or four times per clock tick. However, for efficiency the basic unit of data transfer is a 32 byte "burst" of data around the address of the data the CPU needs. Any CPU reference to memory is rounded up to a complete 32 byte block. This block is transferred in a burst of 4 consecutive 8 byte transfers. Your timing settings effect this transfer, not the Command per clock.

The Command Per Clock sets the Command Rate for the memory controller. At 1T, the controller can issue commands on every clock cycle, if set to 2T the controller can only issue commands only on every other bus cycle. With DDR, the 2T command rate had some poor transferrals since there was little use for the bus interleaving (Dual Channel Mode). Let us say that if you ran at a 2.5 - 3 - 3 latency then the read command would be issued 2 cycles after an bank activate command. This would negate 1T vs 2T correct? Since the issuance was held to 2 cycles there would be no need for a single cycle command rate.

But we have DDR running in Dual Channel Mode and this mode allows for an opening of more than one page in different banks of the same memory device (slots related to dual channel ie. Bank 1 and Bank 3, etc.). So the second bank activate command that follows after the first bank activate command can not be issued since a read command for the first bank has already been scheduled. This is considered a "Bus Contention" and because of it, the next available time slot for the next bank activate command would collide with the second read command for the possibility of a page hit. This would continue until there is a no-op (no operation) return. When there is a no-op return or interval then another bank activate command can be initiated. Because of this issue, dual channel is largely useless, not only is it useless but it can even slow bank activation. This issue follows with DDR2 but one of the reasons for the creation of the DDR2 standard was to eliminate this previously mentioned bus contention. The DDR2 standard created the Posted CAS characteristic, so that there was no need to wait for the Trcd function to be completed. The Posted CAS feature allowed for the Read command to be issued immediately after the bank activate command. But this "Feature" can only be useful with a 1T command rate since a 2T command rate would eliminate the use of this characteristic.

Thus in a DDR2 system, with dual channel bank interleaving enabled there will be a more responsive system. Now there are added latancy issues with DDR2 vs DDR1 so for this benefit to be more effectively seen, one needs very low latency DDR2 DRAM.

When one compares DDR at 3 - 4 - 4 - 8 and DDR2 at 3 - 4 - 4 - 8 (Both Dual channel, bank interleaved) there becomes no doubt that the DDR2 is a far better memory transaction at 1T vs 2T and the difference at the DDR level is far less pronounced.

So, don't expect miracles with DDR and 1T but with (high quality and low timing) DDR2 you can expect a far greater response from 1T vs 2T.

R
Holy crap

Didn't think you would post that much but I get that now thanks for posting it up REP+


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post #7 of 9
Quote:
Originally Posted by Unknownm View Post
Unknownm
I don't think I've been told I talk too much so nicely. j/k
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post #8 of 9
Ropey talk too much? No way. I don't believe it!
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post #9 of 9
I should add though that he is extremely helpful (most of the time). And he has gone through great lengths in just helping me to understand different things.

So thanks for always bearing with me Ropey and I appreciate any/all the help you've ever offered me.
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