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[Sweclockers] - AMD prepares FX-9000 up to 5.0 GHz - Page 79

post #781 of 953
Quote:
Originally Posted by keiths View Post

So the doubling of all the units only result in a 30% improvement or different speculations?
Could be more. As well as reducing branch mispredictions, which bugged BD not entirely sure about K10.5 but this is one of the biggest problems of BD
Excavator's to fix the L3 cache uselessness (aka massive latency tongue.gif) which has bugged AMD ever since K10
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post #782 of 953
Quote:
Originally Posted by keiths View Post

So the doubling of all the units only result in a 30% improvement or different speculations?

The only thing doubled is the decoders. There is still the single prefetch, shared L2, etc. The doubled decoder removes the bottleneck where 2 cores perform at about 1.6-1.8x performance of a single core instead of 2x performance.

Edit: Well, it's not the only thing doubled, but it is the biggest change.
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post #783 of 953
Quote:
Originally Posted by Tsumi View Post

The only thing doubled is the decoders. There is still the single prefetch, shared L2, etc. The doubled decoder removes the bottleneck where 2 cores perform at about 1.6-1.8x performance of a single core instead of 2x performance.

Edit: Well, it's not the only thing doubled, but it is the biggest change.
The decoders:
Single - Single - Single - Single
or
Double - Single - Single

Double - 256-bit vector instructions
Single - 128-bit vector instructions

The doubling of the decoders in Steamroller is not because the decoders were a bottleneck for Bulldozer. The doubling of decoders is because of the module of Steamroller will have 8 ALUs/8 AGUs/8 VALUs where Bulldozer has 4 ALUs/4 AGUs/4 VALUs.

What else has been doubled:
Instruction Fetch/Prefetch(Two seperate duplicate engines)
Instruction L1 Cache(2x64KB or 1x128KB)
Instruction Decoders(SSSS/SSSS or DSS/DSS)
General Purpose x86-64 Logic
Load-Store Bus?
Data L1 Cache(16 KB -> 32 KB)
Vector x86-64 Logic(FPU)

Also, the Cluster Multithreading numbers Pre-Bulldozer launch are: (-> actual benchmarks)
Module, Single Core(Maxed): Core 0 100% performance, Core 1 000% performance(off) -> Which leads to only 80% usage of all resources.
Module, Dual Core(Both Maxed): Core 0 90% performance, Core 2 90% performance -> Which leads to >95% usage of all resources.
Also, to note that 10% loss in both cores are returned with access to the same pool of memory. (L1i/L2)
Edited by Seronx - 6/12/13 at 3:24am
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post #784 of 953
So, not only they double the decoders, but also all the logic?

Then single threaded performance does actually look it can match what AMD hinted...


Just a thought, if they double the decoders, but also the rest of the logic, one decoder will still feed two ALUs/AGUs right?

Thanks for the explanations Seronx smile.gif
   
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post #785 of 953
Quote:
Originally Posted by keiths View Post

So the doubling of all the units only result in a 30% improvement or different speculations?

At Computex 2013, AMD said that steamroller will have only 15 to 20% IPC improvement

http://www.tomshardware.com/news/AMD-Kaveri-APU-Gaming,22947.html
http://wccftech.com/amd-demonstrates-fourth-generation-kaveri-apu-computex-2013-ruby-techdemo-showcased/

People expecting this to be 30% faster are going to be very disappointed. I would not be surprised if actual improvement is lower than what AMD claims.
post #786 of 953
Quote:
Originally Posted by Blameless View Post

I agree the emphasis should be on overall performance, but single threaded performance is still the limiting factor in many real scenarios.
Not so much...

Steamroller will improve mutli-threaded performance far more than single threaded performance.

That 30% performance boost everyone is talking about will likely only be seen in heavily threaded tasks.

The biggest (though far from only) change to steamroller is widening the front-end, and the front-end is already wide enough to accommodate one core per module without a bottleneck. Thus, if you are running equal or fewer threads than the number of modules you have, you will likely see a much more modest improvement.
Not accurate at all. Doubling the decoders benefits single threaded apps equally to multithreaded.Shortening the IMC benefits single-threaded apps as well. There are a few other tweaks that may benefit multi-threaded apps more. I would venture to guess at least 15%-20% improvement for single threaded apps and 20-25% for multithreaded apps. That should put the flagship steamroller chip better than the I7 4770k in overall performance for a lower price. It will lag a bit in single threaded performance but be significantly better in multi-threaded. Intel does have something to worry about. They are lagging in innovation.
Edited by os2wiz - 6/12/13 at 4:50am
post #787 of 953
I'm not sure how you figure doubling the decoders will help single threaded performance very much. The decoder each module already has in BD and PD is very capable and able to keep a single core loaded. It was just insufficient to feed two cores to maximum potential. There are other improvements to the architecture that will yield single threaded performance improvements, but that just isn't going to be one of the big ones. I'd more expect overall instructions per second to increase as well as instructions per module per second when dealing with code that has more than one thread executing on a single module when talking about the decoder change.
post #788 of 953
Is 5ghz boost on all cores or just 2? Or even 1....
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post #789 of 953
Quote:
Originally Posted by os2wiz View Post

Not accurate at all. Doubling the decoders benefits single threaded apps equally to multithreaded.Shortening the IMC benefits single-threaded apps as well. There are a few other tweaks that may benefit multi-threaded apps more. I would venture to guess at least 15%-20% improvement for single threaded apps and 20-25% for multithreaded apps. That should put the flagship steamroller chip better than the I7 4770k in overall performance for a lower price. It will lag a bit in single threaded performance but be significantly better in multi-threaded. Intel does have something to worry about. They are lagging in innovation.

If all that you said happens and even happens to be better than your estimation then Steamroller is well earned name for 3rd gen Bulldozer...

If AMD fixes L3 cache problem with Excavator, what we can expect in terms of performance?
post #790 of 953
Quote:
Originally Posted by lacrossewacker View Post

Is 5ghz boost on all cores or just 2? Or even 1....

I'd expect it to be on one. Something like 4.7 base, 4.8 to 2-4 cores, 5 to just one.
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