c3 would drop vcore. C6/C7 is almost useless in terms of power savings, EIST will allow drop to 800mhz, C1E is like EIST.
also no gigabyte is adaptive, not manual override, but you can use adaptive like offset if you enable C3 state it will drop the VCore, but on newer CPUz versions(cpuz1.64.0 should be okay, but 1.65 will show VID not VCOre). Every CPU is different but it adds as much voltage as it needs when AVX is used, I mean what program you use in real life that uses AVX other than these stability test?
If your temp is going high then take a digital multimeter and read the vcore from the read points.VIN on auto will also might go up and increase temps.
Intel integrated two clock generators into the CPU, two different clock generator types, one is SBPLL and the other is LCPLL, that is just what they code them in the code, I am really not sure what the difference is other than, LCPLL is most steady, like less up and down margin of error, so like if you set 100.00 BCLK is allowed to sway up and down like 0.5% or less, LCPLL will allow less sway. SBPLL however will allow higher margin. So at default I think the board sets LCPLL and low filter, but I am not sure, it really doesn't matter much, I wouldn't mess with it, they know what they are doing with auto.
Filter level is how much the signal is filtered, if you are at high BCLK then you need a higher level of filtering b/c of the increase in jitter, but at lower BCLK the jitter is less and thus you don't need an overcompensating filter level. Same thing, BIOS guys auto rules work well.
With the latest FINAL BIOSes released in the past week or two, you guys shoudl be able to do pretty high BCLK even without the OC board, but only with 1.00x an 1.25x dividers, they will add in support for high BCLK and 1.67x divider very soon.
On the UD3H I can o 118.7 x 1.00x divider with BIOS F6 while BIOS F4 I couldn't. However this entails pretty long BCLK training, so you will see the board go from 15-95 over and over, maybe 7 -10 times and then it will finally boot. If you use high BCLK like this it will do this every time you change the BCLK, this is DMI/BCLK training. High BCLk like that tho is only useful for memory OC over 4ghz(4ghz memory I mean). Also that training procedure will get better over time, like on the OC board it only reboots once or twice and can do almost 200mhz on air now, that is how the UD3H and othe boards will be soon(all this with those PLL selections and levels on auto). A tip for BCLK OC: Lower your PCH IO from 1.5v to 1.2v