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post #1271 of 3492
Quote:
Originally Posted by Kuivamaa View Post

Because I have use for 8 threads obviously? Octocores have higher ipc than quad intels on fully multithreaded scenarios as well.

hehe this
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post #1272 of 3492
I would be in you guys' boat if I did lots of work with heavily-threaded apps, lol. The main CPU-intensive tasks I do on my PC are emulation, so all I desire is higher single-threaded perf and a quad-core Kaveri will give me that. thumb.gif
post #1273 of 3492
I have to agree with a lot of the above posts. With 290x and its bandwidth and Mantle games that will support more than 4 cores it would not make sense for AMD to not release an enthusiast 6-8 core part to capitalize on the success that this could bring. So I think this is what is possible.

I think AMD is keeping their lips sealed shut to avoid another Bulldozer hype and fail fiasco again. Just because we as the end consumer have not heard anything does not mean that AMD is not developing something.

So with that in mind I have some scenarios that have come to mind. 990FX although old is by no means incapable. It can support 2 full PCI-E 2.0 at 16x which = PCI-E 3.0 at 8x. But we know that even with current GFX we are not saturating 2.0. HOWEVER we might saturate 2.0 if SLI and CFX loose the bridges and migrate to PCI-E lanes. Ok so 990FX gets refreshed for a hypothetical SR FX chip. What is stopping Mobo manufactures from adding nVidia NF200 chips to add a few more PCI-E lanes so that you can run triple or quad fire at 16x? So my scenarios are as follows:

Scenario 1: 990FX refresh with AM3+ and SR FX. Motherboard makers support 3.0 like Saberkitty GEN3 or add NF 200 chips to increase PCI-E lanes.
Scenario 2: 990FX and AM3+ decommissioned. Possible 88FX chipset for FM2+ We already have 88x so I am basing on the same lines of 990x and 990FX. AMD releases SR based CPU on FM2+ WITHOUT I-GPU to save space for more modules.
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post #1274 of 3492
I think many people are not understanding how PCIe works on the 990FX (and previous) platforms. Even though the chipset provides 4 x16 PCIe 2.0 lanes, the link between the chipset and the CPU is a single HT 3 link which provides less than half the bandwidth (25.6GB/s) of all of the lanes combined. It is the very definition of a bottleneck.

Not to mention that PCIe already has relatively high latency. An additional hop (the chipset) for packets between the CPU and GPU makes latency even worse.

FM2+ is superior in this regard because is 16 PCIe 3.0 lanes provided by an on-die controller - thats a full 32GB/s of bandwidth and as low latency for PCIe traffic as the standard will allow. These lanes are dedicated for graphics, and there are additional lanes for SSDs and connections to the chipset for LAN,SATA etc. On AM3+, the HT link bandwidth is used for all system I/O.

In short AMD does this for the same reason that they added the on-die memory controller.
Quote:
Originally Posted by Alastair View Post

I have to agree with a lot of the above posts. With 290x and its bandwidth and Mantle games that will support more than 4 cores it would not make sense for AMD to not release an enthusiast 6-8 core part to capitalize on the success that this could bring. So I think this is what is possible.

I think AMD is keeping their lips sealed shut to avoid another Bulldozer hype and fail fiasco again. Just because we as the end consumer have not heard anything does not mean that AMD is not developing something.

So with that in mind I have some scenarios that have come to mind. 990FX although old is by no means incapable. It can support 2 full PCI-E 2.0 at 16x which = PCI-E 3.0 at 8x. But we know that even with current GFX we are not saturating 2.0. HOWEVER we might saturate 2.0 if SLI and CFX loose the bridges and migrate to PCI-E lanes. Ok so 990FX gets refreshed for a hypothetical SR FX chip. What is stopping Mobo manufactures from adding nVidia NF200 chips to add a few more PCI-E lanes so that you can run triple or quad fire at 16x? So my scenarios are as follows:

Scenario 1: 990FX refresh with AM3+ and SR FX. Motherboard makers support 3.0 like Saberkitty GEN3 or add NF 200 chips to increase PCI-E lanes.
Scenario 2: 990FX and AM3+ decommissioned. Possible 88FX chipset for FM2+ We already have 88x so I am basing on the same lines of 990x and 990FX. AMD releases SR based CPU on FM2+ WITHOUT I-GPU to save space for more modules.
post #1275 of 3492
Quote:
Originally Posted by Kuivamaa View Post

Even If top A10 absolutely matches an i5-3570k I am still going FX-8350.[/quote

No need to worry about that, I can assure you that the top steamroller 4 core APU will not equal a I5 3570k in multi-threaded performance and will be a smidgeon short of equaling it in single thread performance. Only AFTERwide-spread adoption of HSA (2-3 years) will that apu really shine.
post #1276 of 3492
Quote:
Originally Posted by MrJava View Post

I think many people are not understanding how PCIe works on the 990FX (and previous) platforms. Even though the chipset provides 4 x16 PCIe 2.0 lanes, the link between the chipset and the CPU is a single HT 3 link which provides less than half the bandwidth (25.6GB/s) of all of the lanes combined. It is the very definition of a bottleneck.

Not to mention that PCIe already has relatively high latency. An additional hop (the chipset) for packets between the CPU and GPU makes latency even worse.

FM2+ is superior in this regard because is 16 PCIe 3.0 lanes provided by an on-die controller - thats a full 32GB/s of bandwidth and as low latency for PCIe traffic as the standard will allow. These lanes are dedicated for graphics, and there are additional lanes for SSDs and connections to the chipset for LAN,SATA etc. On AM3+, the HT link bandwidth is used for all system I/O.

In short AMD does this for the same reason that they added the on-die memory controller.


I said the A88X chipset can be used on AM3+ and I stick to that. That would eliminate that issue on AM3+ so no need to harp on why you would need to switch to FM2+ right away. Of course you would need a new motherboard , so that negates the benefit for AM3+ to a large extent.
post #1277 of 3492
Uh, no it wouldn't. The A88X chipset does not handle the connection between CPU and GPU, there is a direct connection between CPU and GPU because of the on-die PCIe controller.
The A88X chipset only handles LAN, SATA and USB and is connected to the CPU via a separate x4 PCIe interface.
Quote:
Originally Posted by os2wiz View Post

I said the A88X chipset can be used on AM3+ and I stick to that. That would eliminate that issue on AM3+ so no need to harp on why you would need to switch to FM2+ right away. Of course you would need a new motherboard , so that negates the benefit for AM3+ to a large extent.
post #1278 of 3492
Quote:
Originally Posted by MrJava View Post

I think many people are not understanding how PCIe works on the 990FX (and previous) platforms. Even though the chipset provides 4 x16 PCIe 2.0 lanes, the link between the chipset and the CPU is a single HT 3 link which provides less than half the bandwidth (25.6GB/s) of all of the lanes combined. It is the very definition of a bottleneck.

Not to mention that PCIe already has relatively high latency. An additional hop (the chipset) for packets between the CPU and GPU makes latency even worse.

FM2+ is superior in this regard because is 16 PCIe 3.0 lanes provided by an on-die controller - thats a full 32GB/s of bandwidth and as low latency for PCIe traffic as the standard will allow. These lanes are dedicated for graphics, and there are additional lanes for SSDs and connections to the chipset for LAN,SATA etc. On AM3+, the HT link bandwidth is used for all system I/O.

In short AMD does this for the same reason that they added the on-die memory controller.



Well I guess we are back to this discussion again biggrin.gif

Here is the thing though, the current implementation of 990FX platform with its HT3.1 controller and PCI-E lanes IS inadequate. This however can be fully fixed if a new CPU were released for the platform so the argument about not using AM3+ is completely invalid. The new CPU *could* have PCI-E 3.0 lanes on-die, but it still wouldnt need it. Those PCI-E lanes take up a decent bit of space, a bit more than HTT IO would. Furthermore if AMD were to actually use the HT links for the PCI-E traffic then it would take no additional space because there are already four 16-bit HT 3.1 controllers on die. All AMD has to do is increase these to 32-bit (which is the same as integrating PCI-E controllers anyway so no matter what your view this change in die space would already be taking place) and the HT 3.1 lanes would have more bandwidth than the PCI-E 3.0 lanes would. There is no need for a hop to northbridge even with no PCI-E controllers at all, the HT controller is directly map-able to PCI-E addresses. A 32-bit HT IO controller is equivalent in size and ability to a 32-bit x16 PCI-E 3.0 controller, however the HT link has lower latency and more bandwidth. Using the same HT links, only increased to 32-bit bus, would alleviate all bandwidth issues on the current 990FX platform, have directly on-die integrated "PCI-E" only with better performance, and still have room left over for a southbridge connection. AMD also already uses four separate HT link controllers which means this would be the equivalent of 64 PCI-E 3.0 lanes on-die. It also allows AMD to not change their server designs and lets the new CPUs be drop in compatible to current platforms because it still uses HT links so the inter CPU communication would be done the same on multi-CPU systems. There isnt a single drawback to this design other than the increased die space, but that doesn't matter cause even if HT links were dropped the same die space would be taken by the PCI-E links.


For easy reference:
A 32-bit HT link has 51.2 GB/s of bandwidth.
32-bit 16 lane PCI-E 3.0 has 31.5GB/s of bandwidth


And before anyone asks, yes a HT link can be split up exactly the same for smaller "lanes" just like PCI-E can and is still directly map-able.
Edited by EniGma1987 - 10/28/13 at 10:25am
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post #1279 of 3492
1. But then you would still need a chipset to translate between HT (one protocol) and PCIe (another) which adds latency.
2. C32 uses 1200+ pins for 2 HT 3.1 Links. G34 uses 1900+ pins for 4 HT 3.1 links. AM3+ is not sufficient for this amount of I/O, otherwise it would've been enabled from the start.

So if you want to fix any of the problems of the current platform, you need a new socket and new motherboard. Does that sound like FM2+ or the hypothetical FM3 to anyone.
post #1280 of 3492
Quote:
Originally Posted by MrJava View Post

1. But then you would still need a chipset to translate between HT (one protocol) and PCIe (another) which adds latency.
2. C32 uses 1200+ pins for 2 HT 3.1 Links. G34 uses 1900+ pins for 4 HT 3.1 links. AM3+ is not sufficient for this amount of I/O, otherwise it would've been enabled from the start.

So if you want to fix any of the problems of the current platform, you need a new socket and new motherboard. Does that sound like FM2+ or the hypothetical FM3 to anyone.

I suppose your right on that second part. Although just how many more pins are needed only AMD would know. It has to be significant at least because otherwise each socket wouldn't increase so drastically. I would like to throw another thought out there though going off what you just brought up, the same situation is really true for either AM3+ or FM2+ here. FM2 has even less pins, so although you couldnt use 4 full HT links, you also wouldnt be able to use a huge number of on-die PCI-E links. If FM2+ has room for 16 on-die lanes then AM3+ would be able to do just as many and possibly a bit more because it has more pins. But your right on the 4 full links, definitely not enough pins for that.


Why would you need a chipset to translate? The hyper transport controller is already directly map-able to PCI-E and translates any encoding difference in the controller. Since this is the case, do we really still need something else in between? Doesnt seem like it to me.
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