Originally Posted by MrJava
I think many people are not understanding how PCIe works on the 990FX (and previous) platforms. Even though the chipset provides 4 x16 PCIe 2.0 lanes, the link between the chipset and the CPU is a single HT 3 link which provides less than half the bandwidth (25.6GB/s) of all of the lanes combined. It is the very definition of a bottleneck.
Not to mention that PCIe already has relatively high latency. An additional hop (the chipset) for packets between the CPU and GPU makes latency even worse.
FM2+ is superior in this regard because is 16 PCIe 3.0 lanes provided by an on-die controller - thats a full 32GB/s of bandwidth and as low latency for PCIe traffic as the standard will allow. These lanes are dedicated for graphics, and there are additional lanes for SSDs and connections to the chipset for LAN,SATA etc. On AM3+, the HT link bandwidth is used for all system I/O.
In short AMD does this for the same reason that they added the on-die memory controller.
Well I guess we are back to this discussion again
Here is the thing though, the current implementation of 990FX platform with its HT3.1 controller and PCI-E lanes IS
inadequate. This however can be fully fixed if a new CPU were released for the platform so the argument about not using AM3+ is completely invalid. The new CPU *could* have PCI-E 3.0 lanes on-die, but it still wouldnt need it. Those PCI-E lanes take up a decent bit of space, a bit more than HTT IO would. Furthermore if AMD were to actually use the HT links for the PCI-E traffic then it would take no additional space because there are already four 16-bit HT 3.1 controllers on die. All AMD has to do is increase these to 32-bit (which is the same as integrating PCI-E controllers anyway so no matter what your view this change in die space would already be taking place) and the HT 3.1 lanes would have more bandwidth than the PCI-E 3.0 lanes would. There is no need for a hop to northbridge even with no PCI-E controllers at all, the HT controller is directly map-able to PCI-E addresses. A 32-bit HT IO controller is equivalent in size and ability to a 32-bit x16 PCI-E 3.0 controller, however the HT link has lower latency and more bandwidth. Using the same HT links, only increased to 32-bit bus, would alleviate all bandwidth issues on the current 990FX platform, have directly on-die integrated "PCI-E" only with better performance, and still have room left over for a southbridge connection. AMD also already uses four separate HT link controllers which means this would be the equivalent of 64 PCI-E 3.0 lanes on-die. It also allows AMD to not change their server designs and lets the new CPUs be drop in compatible to current platforms because it still uses HT links so the inter CPU communication would be done the same on multi-CPU systems. There isnt a single drawback to this design other than the increased die space, but that doesn't matter cause even if HT links were dropped the same die space would be taken by the PCI-E links.
For easy reference:
A 32-bit HT link has 51.2 GB/s of bandwidth.
32-bit 16 lane PCI-E 3.0 has 31.5GB/s of bandwidth
And before anyone asks, yes a HT link can be split up exactly the same for smaller "lanes" just like PCI-E can and is still directly map-able.Edited by EniGma1987 - 10/28/13 at 10:25am