Originally Posted by Kuivamaa
I thought the idea behind disabling all the "slave" cores of each module was to prevent the OS from erroneously loading two cores of the same module when there were available threads elsewhere, avoiding the "shared resources" penalty.
I am considering the shared decoder as part of the problem. Ergo one core one module means the PD core gets its own decoder.
The news on the caches is great, but I feel like if AMD did release a pure CPU with L3 that the L3 would just be a copy paste job or something.
I think the decoder changes are only going to matter when using multiple threads. I swore I saw someone here or on another forum claiming the opposite.
Found this while searching, had some interesting graphs and such.