Originally Posted by MrJava
Perhaps you should be the one to backup up your claims that HT and PCIe are "directly compatible" (they aren't).
You still didnt provide proof, just your opinion on how the technologies work. As per the Hyper-Transport specifications paper, the HTT controller supports 40-bit re-addressing, direct 8b10b communication from encoding/decoding (which PCI-E 2.1 and lower uses), and a few other things that allow direct communication between HTT controller and PCI-E. Here is just one example from the documents, in a section called "PCI-Express Transaction Mapping to HyperTransport Packets". Ill skip all the table stuff and give you the most important sentence near the beginning: "All PCI Express transactions use a HyperTransport sequence ID of 0. So yes you can map PCI-E addresses and packets directly to HTT address space. There are many other sections about the compatibility and how HTT communicates directly to PCI-E, and there is even an example in one part showing address remapping between HTT controller and PCI-E space. There is even a whole section in an Appendix to the specifications documents that talks about the ordering and command mapping of how PCI-E is done within HyperTransport. Perhaps rather than simply thinking you know so much on this subject you should actually look into the specifications that you are debating against?
BTW, current spec HTT has 51.2GB/s bandwidth, enough to fit a full PCI-E 3.0 lanes within the HTT link. AMD uses an old spec and only half links in their controllers right now. Nothing to stop them from using full spec'ed controller in the future. HTT 4.0 looks to add significantly more bandwidth once again too. By that point it may have enough to support 16x PCI-E 4.0 tech that is coming in the future.
Since AMD already has four half-link HTT controllers on the die, they could use the same die space to put two full link controllers in. This would give 102.4 GB/s of bandwidth, or in other terms: enough for three full x16 PCI-E 3.0 slots plus extra room to spare for southbridge and other I/O.
Edit: oh one more small excerpt from a section I found interesting:
"PCI Express defines Address Translation Services to allow endpoint devices or bridges to improve I/O performance.This appendix provides the HyperTransport packet formats needed to provide these services in systems using HyperTransport links."Edited by EniGma1987 - 11/12/13 at 6:29am