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Steamroller? - Page 316

post #3151 of 3492
Quote:
Originally Posted by heroxoot View Post

How I wish for an 8core APU. If L3 really is a waste of space, then it should be possible if removed right?
Well L3 isn't a waste but in Piledriver it was actually using it made the whole process slower due to major design flaws. If they are not fixed yet it might aswell be removed and replaced with either extra modules or extra graphics blocks.
post #3152 of 3492
The L3$ would've been more effective had the K15 family been devoid of several of the design flaws present in the uarch. Check out Agner's Steamroller analyses here: Link 1 Link 2

It becomes more clear why Steamroller didn't meet the original IPC increase target of ~30%. They barely reached the figure they had on their own revised slides of 20%. There are still many bottlenecks in the design that hamstring the performance. My guess is that the engineers opted to focus moreso on the HSA aspects than going for raw IPC increase. The IPC increase offset the clockspeed reduction compared to previous-gen Richland.

We still hardly know much about Excavator, but hopefully the engineers can find the culprits of these bottlenecks and eliminate them. Either way, I don't expect much from Carrizo -- both on the CPU and GPU front. Best case scenario they increase the raw performance enough on the CPU side to once again offset the clock reductions. In fact, lower clocks and higher IPC is the way to go, since Steamroller v2 performs best at lower clocks (requiring less voltage and consuming less power than its predecessor at the same clocks). Due to the process node, it became painfully clear that AMD's original "longer pipeline, higher clocks" strategy fell flat with Kaveri.
post #3153 of 3492
Quote:
Originally Posted by NaroonGTX View Post

The L3$ would've been more effective had the K15 family been devoid of several of the design flaws present in the uarch.
The 15h family architecture is actually the K10 architecture. 00h = K8, 10h = K9, 15h = K10.



If you go into the hole further you will find out also that the 10h family architecture was planned to be used till it hit 5 GHz. The sad part of 10h and 15h is that the primary people who made those designs are either retired or dead.
Quote:
Originally Posted by NaroonGTX View Post

Due to the process node, it became painfully clear that AMD's original "longer pipeline, higher clocks" strategy fell flat with Kaveri.
The 15h architecture in Kaveri is actually smaller and tighter than the 15h in Trinity and Richland.

To the point where 15h 30h-3Fh and 15h 60h-6Fh could essentially be considered a different architecture. They went from a 15 stage pipeline to a 14+1 stage pipeline with Kaveri.
Quote:
Originally Posted by maarten12100 View Post

An APU has more potential so I doubt we'll see another 4 module chip but it is possible so perhaps excavator will give us some love.
You are right you won't be seeing a non-disabled octo-core 15h die till at least 20nm/14nm.

40h-4Fh which is the successor to 00h(Zambezi) and 02h(Vishera/Centurion); has 16 cores in it's non-disabled form.
Edited by Seronx - 3/24/14 at 4:01pm
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post #3154 of 3492
In some of my earlier posts, I used to call Bulldozer K10, since that's what some engineers called it. Athlon 64 and all of its successors up until Bulldozer were K8, internally. I'm pretty sure enthusiasts were the ones who saw the 10h and 15h, etc. names and just slapped the K in front of the number, which caused the discrepancies back in the day. AMD themselves used the K15 moniker recently to refer to Kaveri in an old cpu-z shot from last year of an eng-sample.
post #3155 of 3492
I still have some K7 athlon and athlonMPs lachen.gif

before my FX-8150 I had an AthlonII 640, effectively a low power variant of the PhenomIIs without L3, t'was a HUGE upgrade to the old Pentium4 extreme I had before it in both single and multi-thread loads, K10 > bulldozer was pretty much the same for me (slightly faster per-core, but twice the core count).
   
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post #3156 of 3492
The L3 is a massive waste of die space.

I'd be interested to see how excavator would perform without L3, and some combination of GCN cores and extra modules.

AMD should have just completely abandoned the single-thread race entirely, ditched the L3, and doubled the number of modules. Well, at least for an FX replacement. 8m/16c SR would have really disrupted things for a lot of people. And it would have been a lot of fun to see the AMD guys posting 8m/16c parts mauling Intels that cost twice as much in multithread and then watching the Intel guys find all the single thread benchmarks they can. It would have made for good forum watching.
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post #3157 of 3492
So is there a profound reason 8mb of L3 takes so much space on the die? Is it just normally large or did they do it wrong? Intel CPU are smaller and they have a lot of L3 on some don't they? Like 6 - 8mb which is close or the same to the FX series.
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post #3158 of 3492
Quote:
Originally Posted by heroxoot View Post

So is there a profound reason 8mb of L3 takes so much space on the die? Is it just normally large or did they do it wrong? Intel CPU are smaller and they have a lot of L3 on some don't they? Like 6 - 8mb which is close or the same to the FX series.
A worse node and a bad read write architecture where the L3 decreases perf. I'm still baffled they kept it for so long. The L3 problems should be fixed we already saw some very nice improvements with Kaveri for L2 perf over Richland.

If excavator has HDL and is that giant doubled up monster along with 20nm maybe.
That would shake things up I like AMD's focus on power efficiency since this way they can scale across al segments and later next generatiom us the module stratigic to create our fx proc.
post #3159 of 3492
Quote:
Originally Posted by heroxoot View Post

So is there a profound reason 8mb of L3 takes so much space on the die? Is it just normally large or did they do it wrong? Intel CPU are smaller and they have a lot of L3 on some don't they? Like 6 - 8mb which is close or the same to the FX series.

Intel's modern chips use small L2 caches and big L3 caches. AMD uses big L2 caches and (on FX) big L3 caches. Even then, AMD's current caches and read/write performance leave much to be desired. Steamroller was a decent improvement over BD/PD in those regards, but could still use some work. L3 cache latency is absolutely abysmal on K15 so far, even worse than Phenom II, and far far behind Intel. That's why so many people call it worthless, because it pretty much is. I guess AMD knew they wouldn't be making anymore chips that weren't APU's, so they decided there was no point in fixing the L3$ performance.

vPqXam9.jpg

L3$ takes up roughly half the die space on Zambezi & Vishera.
Edited by NaroonGTX - 3/25/14 at 9:16pm
post #3160 of 3492
Quote:
Originally Posted by NaroonGTX View Post

Intel's modern chips use small L2 caches and big L3 caches. AMD uses big L2 caches and (on FX) big L3 caches. Even then, AMD's current caches and read/write performance leave much to be desired. Steamroller was a decent improvement over BD/PD in those regards, but could still use some work. L3 cache latency is absolutely abysmal on K15 so far, even worse than Phenom II, and far far behind Intel. That's why so many people call it worthless, because it pretty much is. I guess AMD knew they wouldn't be making anymore chips that weren't APU's, so they decided there was no point in fixing the L3$ performance.

vPqXam9.jpg

L3$ takes up roughly half the die space on Zambezi & Vishera.

Just take out the L3 and replace it with 2 more modules or an IGPU... It's that easy right!!!?

...making processors is so easy, it's like building legos. biggrin.gif
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