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post #3241 of 3492
Everyone has been had!



The Steamroller Leak was actually indeed truthful in some respects. The image above shows that the imgur/discus was indeed quite accurate.

Kaveri / KV-A0 and KV-A1 dark secret is;
EVERYTHING IS DISABLED!

From the 2013 slides, 1050 GFlops were stated but they are not used!

Desktop KV-B0:
CPU: 16 FMACs * 4 Cores * 2 GHz => ~128
GPU: 1024 ALUs * 2 FMA * 0.45 GHz => ~921.6

--
Tahiti's CU: ~5.5 mm²
Hawaii's CU: ~4.9 mm²
Pitcairn's CU: ~4.5 mm²

Everyone failed to notice that apparently the CUs for Kaveri were ~7.1 mm². For a node that is DENSER than Gate Last, it is less dense than Gate Last. This aroused my suspicion that something was awry. It took me three days but I finally uncovered it, 2.41 billion transistors are to dense to be less dense than Gate Last.

So I'll tell you...
Kaveri has 2 x 256-bit Flex FMACs and 1 x 256-bit Flex MMX/Shuffle.

Kaveri has 4 ALUs and 4 AGUs.

Kaveri has two fetch units that apparently can service both picks. (Two cycles per fetch was pretty suspicious)

Kaveri has a 16 CU GPU on die.

Luckily AMD was smart enough to disable the units to give off higher clocks to achieve near the same effect.
Edited by Seronx - 4/20/14 at 4:51am
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post #3242 of 3492
what does this mean?
post #3243 of 3492
Quote:
Originally Posted by nitrubbb View Post

what does this mean?
There was an issue with KV-A0 that didn't allow everything to work properly. Instead of waiting for a fix AMD simply disabled the problem parts which lead to KV-A1. This also allowed for faster time to market while they can always release KV-B0 later which had the fix.

Think about the 480 GTX and 580 GTX timeline. 480 GTX had a BEOL issue which didn't allow 1/8 of the GPU to work. 580 GTX was later released with the fixed BEOL. I assume the same thing happened with Kaveri but at a much larger scale. Instead of scraping the project or waste time developing the fix. AMD disabled pretty much everything till it worked properly, making Kaveri seem to be below expectations. When it was actually BETTER than anyone's expectations.
- Thanks IDC - thumb.gif
Edited by Seronx - 4/20/14 at 5:00am
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post #3244 of 3492
so there is a chance of a A10-7870 or something before carizzo?
post #3245 of 3492
Quote:
Originally Posted by nitrubbb View Post

so there is a chance of a A10-7870 or something before carizzo?
So far KV-B0 has only been confirmed in the mobile/embedded space.

A10-78x0M with R9 G3xx/G2xx graphics.

If KV-B0 comes out for desktops it could be A10-8870K. With Carrizo being A10-9880K, but I think with Carrizo we will get a new moniker.

FX/Opteron 40h-4Fh and Carrizo 60h-6Fh, will bear a unified moniker. (When I state will, I mean I think heavily that AMD will use a unified moniker)

FX for FX.
P for Opteron.
A for Accelerated.

FX16 - 170
P16 - 170
A10 - 170

Something like this^.

For those wondering, if I am right 28nm SHP is 1/8th node from 22nm SOI (IBM) and 1/4th node from 20nm LPM (CPA). The node is super dense for what AMD got. It's not as dense as 22nm SOI but it is very close to it.
Edited by Seronx - 4/20/14 at 5:31am
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post #3246 of 3492
So basically, you're claiming that AMD released Kaveri on desktop first to offload junk chips it can't do much with and we're going to get a supercharged mobile Kaveri?

http://www.cpu-world.com/CPUs/Bulldozer/AMD-A10-Series%20A10-7850K.html

Kaveri we have now is KV-A1. I always thought KV-A series were meant for an abandoned process.

Well, maybe it is. We have a SteamrollerB that's talked about but I don't think that's the stepping it's referring to as I see things in google telling me desktop Kaveri is SteamrollerB but it has KV-A1 stepping.

So what exactly is desktop Kaveri? A gimped version of a backup plan?

We have SteamrollerB stepping A1. And you're saying there's going to be a SteamrollerB B0 or B1 or something?

If that's true then Steamroller has one god awful secret history behind it. Maybe that has more to do with why we have no Steamroller FX class chips? Things went downhill with Steamroller A, switched to Steamroller B, and then found A0 and A1 had problems? So AMD just salvaged what they could for the time being and are postponing everything? When a chip goes wrong, you want the smallest dies possible, which could explain 2m/4c limit for Steamroller so far.

So really we might actually end up with a Steamroller FX class CPU some time once they get things sorted out? But I'd assume they'd want a new platform for that which more aligned with their HSA goals and was more competitive with Intel's offerings than AM3+ and 990FX chipset?

I think the biggest piece of evidence against this is that AMD historically has never been able to keep secrets like completely screw ups like this hidden. But then again they'd start bragging about things and talking about they have a superior product and they haven't done that with Kabini, 290x, 295x2, etc.

Your theory you're putting forth at least might provide some evidence as to why we have SteamrollerB instead of Steamroller and why we only have a limited Steamroller lineup.
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post #3247 of 3492
Quote:
Originally Posted by sdlvx View Post

So basically, you're claiming that AMD released Kaveri on desktop first to offload junk chips it can't do much with and we're going to get a supercharged mobile Kaveri?
KV-A0 was "supercharged" but it had broken pieces. While AMD implements a fix and later releases KV-B0. AMD decided to come out with KV-A1 which instead of an IPC increase had a clock rate increase.
Quote:
Originally Posted by sdlvx View Post

http://www.cpu-world.com/CPUs/Bulldozer/AMD-A10-Series%20A10-7850K.html

Kaveri we have now is KV-A1. I always thought KV-A series were meant for an abandoned process.

Well, maybe it is. We have a SteamrollerB that's talked about but I don't think that's the stepping it's referring to as I see things in google telling me desktop Kaveri is SteamrollerB but it has KV-A1 stepping.

So what exactly is desktop Kaveri? A gimped version of a backup plan?
All versions of Kaveri after KV-A0 and before KV-B0 are gimped. The launch of KV-A1 is meant to match their time to market requirements.
Quote:
Originally Posted by sdlvx View Post

We have SteamrollerB stepping A1. And you're saying there's going to be a SteamrollerB B0 or B1 or something?
We will have KV-B0 on the mobile front, it should be out by the back to school season.
Quote:
Originally Posted by sdlvx View Post

If that's true then Steamroller has one god awful secret history behind it. Maybe that has more to do with why we have no Steamroller FX class chips? Things went downhill with Steamroller A, switched to Steamroller B, and then found A0 and A1 had problems? So AMD just salvaged what they could for the time being and are postponing everything? When a chip goes wrong, you want the smallest dies possible, which could explain 2m/4c limit for Steamroller so far.

So really we might actually end up with a Steamroller FX class CPU some time once they get things sorted out? But I'd assume they'd want a new platform for that which more aligned with their HSA goals and was more competitive with Intel's offerings than AM3+ and 990FX chipset?

I think the biggest piece of evidence against this is that AMD historically has never been able to keep secrets like completely screw ups like this hidden. But then again they'd start bragging about things and talking about they have a superior product and they haven't done that with Kabini, 290x, 295x2, etc.

Your theory you're putting forth at least might provide some evidence as to why we have SteamrollerB instead of Steamroller and why we only have a limited Steamroller lineup.
SteamrollerA was not competitive to the market, SteamrollerB gimped though gives off the same performance as SteamrollerA. I think if Intel launched Broadwell with better than graphics of KV-A1, AMD would rush to launch KV-B0, which has double the GPU resources. Since SteamrollerB is meant to compete with Haswell. Since, Haswell hasn't launched yet in the server market, AMD could then wait for it then launch a fully active SteamrollerB core server/enthusiast SKU..

So the FX-Opteron is either on 28nm-SHP or some node below it.

----
Where SteamrollerB was an increase in parallel instructions executed, IPC. (Better Parallelization)
Excavator on 20nm should be an increase in clock rate and instruction set extensions. (Better Performance)

Which leads to doubt should FX/Opteron for 40h-4Fh be SteamrollerB(28nm) or Excavator(20nm). I think it could be both since it makes since but the die size is pretty big.

30 mm² * 8 => 240mm² * 2 (To include uncore and L3) => 480 mm²

With the shrink to Excavator, it should be ~200 mm² for 14-nm FDSOI and or ~300 mm² for 20nm-LPM.
Edited by Seronx - 4/20/14 at 11:22am
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post #3248 of 3492
wait so you are claiming that half the chip is disabled?
post #3249 of 3492
Quote:
Originally Posted by monstercameron View Post

wait so you are claiming that half the chip is disabled?
Quote:
According to Agner, “ Two of the pipes have all the integer execution units while the other two pipes are used only for memory read instructions and address generation (not LEA), and on some models for simple register moves. This means that the processor can execute only two integer ALU instructions per clock cycle, where previous models can execute three. This is a serious bottleneck for pure integer code. The single-core throughput for integer code can actually be doubled by doing half of the instructions in vector registers, even if only one element of each vector is used.”

This has been the case since Bulldozer debuted — but issues here could explain why integer performance on Steamroller is so low compared to other cores. This is where things become frustratingly opaque — each of the areas we’ve identified could be the principle bottleneck — or it’s possible that the bottleneck is a combination of multiple factors (long pipelines, low fetch, cache collisions and low integer performance).

http://www.extremetech.com/computing/177099-secrets-of-steamroller-digging-deep-into-amds-next-gen-core/3

Basically, Seronx is claiming that AMD added more ALU and AGUs (the things that do math) but they didn't work properly, so most of them are disabled.

I guess to put it as the infamous and often horrible car analogy, it's like having an engine that has 8 cylinders and 8 carburettors but half the carbs are messed up so you just use 4 of them.

There are musings at S|A about how the extra IMC on Kaveri might end up getting turned on and we might see GDDR5 mobile parts as well. A fully HSA enabled laptop with 8GB of GDDR5 sounds pretty awesome, actually. It'd be rather ironic if your laptop ended up being faster than a high end Intel CPU setup when you're using HSA on the AMD and Intel can't use it.

But seronx isn't the only one making claims that mobile Kaveri is going to have something new and exciting. I do agree, there's things on the die that don't make sense and the fact that AMD has a chip that's seemingly using a mobile oriented process (the chip scales horribly when you go to high frequency but it's absolutely fantastic low). It just doesn't add up entirely for it to be a solid desktop chip.
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post #3250 of 3492
Quote:
Originally Posted by monstercameron View Post

wait so you are claiming that half the chip is disabled?
I have claimed and provided proofs that indeed Kaveri is half disabled. So I'll move on to other subjects probably to stumble on why.

First: 28nm-SHP.

GlobalFoundries 32nm-SHP;
130nm CPP => 32.5nm Lgate
104nm 1x metal layers, single patterning

TSMC's 28nm and GlobalFoundries CPA 28-nm; TSMC28HP/HPL/HPM , GF28HPP/HP/LPH/LPS/SLP
~120nm CPP => 30nm Lgate
~90nm 1x metal layers, single patterning

There is no way for a design from TSMC or CPA to nearly double all the transistors from 32nm-SHP;
Richland -> 246 mm² / 1.3 billion
Kaveri -> 245 mm² / 2.41 billion

If AMD used TSMC or CPA nodes at best there would only be a die shrink; ~210 mm² @ 1.3 billion. While if more transistors; ~250+ mm² @ 1.5 billion. The majority of 28nm nodes do not provide the density Kaveri actually has.

So, I bring to you the actual specifications of 28nm-SHP:

GlobalFoundries 28nm-SHP;
100nm CPP => 25nm Lgate
80nm 1x metal layers, double patterning

As you can tell it is the bulk node of 22nm.

----
Knowing this now there can only be two problems that AMD could have had with the initial KV-A0;
1st: A bad BEOL design or a BEOL defect, either AMD or GlobalFoundries.
2nd: Device variations where very few of the parts hit targets for parametric yields. Again, could be AMD or GlobalFoundries.

So, instead of cancelling the product or delaying the launch for the fix. AMD decided to die harvest half the die and simply sell on the power efficiency aspect; which is KV-A1. While, they work meticulously to solve the issues then with a new spin, KB-B0 which has the full die enabled.
Quote:
Originally Posted by sdlvx View Post

There are musings at S|A about how the extra IMC on Kaveri might end up getting turned on and we might see GDDR5 mobile parts as well. A fully HSA enabled laptop with 8GB of GDDR5 sounds pretty awesome, actually. It'd be rather ironic if your laptop ended up being faster than a high end Intel CPU setup when you're using HSA on the AMD and Intel can't use it.
I'll tell you that is probably not the case.

I don't think the IMC can be full GDDR5;

128-bit DDR3 and 128-bit GDDR5 or 256-bit DDR3. The language of the BKDG for 30h-3Fh kind of implies the second phy is the only one with GDDR5 mode.

8 GB DDR3 + 2 GB GDDR5.
or
16 GB DDR3.

In both cases, hUMA is enabled and any required move between the RAM interfaces is offloaded. Each interface is coherent of each other and is aware what the other one has.

KV-B0's functionality also doesn't work with; FM2+ or FP3.

While the Carrizo (60h-6Fh) leak talked about SP2. Which I think is a much bigger BGA and Kaveri 2.0 uses it as SP1. If Kaveri uses SP1 it means that there is also a southbridge on die as well. With that I think AMD will be releasing a desktop version with an SM1 socket.

FMx (PGA) = FPx (BGA)
SMx (LGA) = SPx (BGA)

Kaveri/Carrizo 1.0s (die harvested parts) => FMx/FPx
Kaveri/Carrizo 2.0s (full enabled parts) => SMx/SPx

That means AMD could have intentionally done this for segmentation. While also AMD could be preparing for the same thing to happen at the lower nodes as well.

1H 201x = 1.0s
2H 201x = 2.0s

Kaveri (28nm-SHP) and Carrizo (20nm/14nm) are the same device on different nodes. Equivalent to Agena on 65-nm and Deneb on 45-nm. I clearly remember Agena SKUs being on AM2 and AM2+ and Deneb SKUs being AM2+ and AM3.
----
Then, we have to consider KV-A1 to KV-B0 to be similar to OR-B2 to OR-C0.

KV-Ax = bdver3
KV-B0 = bdver4
Carrzio - Ax = bdver4
Carrizo - Bx = bdver5
Basilisk - Ax = bdver5
Edited by Seronx - 4/21/14 at 9:47am
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