From the Linux Kernel Mailing List: https://lkml.org/lkml/2013/8/2/516
Adding support for handling ECC error decoding for new F15 models.
On newer models, support has been included for upto 4 DCT's,
however, only DCT0 and DCT3 are currently configured. (Refer BKDG Section 2.10)
There is also a new "Routing DRAM Requests" algorithm for this model.
So the 4 DCT (DRAM Controller) rumor basically applies to future APUs (probably Carizzo). A few ways of interpretting the above:
1. 4 DCTs on Kaveri die, two are disabled
2. 2 DCTs are present on Kaveri die, but northbridge supports up to 4
I'd say number two would make sense so that AMD would not have to re-engineer the northbridge to support quad channel DDR3/4; they would only need to change the memory controller.
From SiSoft: http://www.sisoftware.eu/rank2011d/show_run.php?q=c2ffcdf4d2b3d2efdee7d0e4dcedcbb984b492f792af9fb9caf7cf&l=en
Benchmark result for Kaveri variant with 832SP or 13CU. Appears in a device called BANTRY which is the codename for the Kaveri reference platform.
"KV SPECTRE DESKTOP 100W (1305); AMD Radeon R5 M200 Series (832SP 13C 600MHz, 3GB DDR3 1.6GHz 64-bit, Integrated Graphics) (OpenCL)"
Edit: Doh, the above is probably just a low end radeon card in kaveri test system.Edited by MrJava - 9/20/13 at 1:25pm