Firstly, for the people who are under the impression that Cinebench supports AVX, I want you all to acknowledge that Cinebench 11.5 doesn't know anything about AVX.
Cinebench 11.5 had been compiled using old ICC 11.0 (Intel C++ Compiler version 11.0 launched in year 2008 that supported all SSE extensions, and knew nothing about AVX ), The very first compiler that supports AVX is ICC 11.1 to newer compiler versions.
We did not expect that the latest Opteron would outperform the previous one by a large margin. Cinebench is limited by SSE processing power. The ICC 11.0 compiler was the fastest compiler of its time for SSE/FP intensive software, even for the Opterons (up to 24% faster than the competing compilers), but it has no knowledge of newer architectures. And of course, the intel compiler does favor the Xeons.
But it doesn't change the fact that Intel was and still is very much afraid of AMD CPU's actual performance,
As you know Cinebench 11.5 is utilizing SSE instruction sets (SSE, SSE2, SSE3, SSSE3 and SSE4.1).
And All AMD Bulldozer/Piledriver CPUs fully support these instructions, but Intel has stll been using unfair CPU dispatcher for any non Intel CPUs. That means no CPU can use these instructions unless the CPU is an Intel Genuine.
However version 11.0 is not in here but it shows how Intel compiler actually works for non Intel CPUs.
All the software that were/are and will be compiled using these compilers force AMD CPUs to use that old SSE2 extension ONLY, that consumes very large amount of transistors switching frequency than currently available SSE4.2/AVX/FMA extensions. This is the only reason AMD is providing us a CPU that runs with much higher frequency than Intel (eg. 3.4GHz 2600k vs 4.0 GHz 8350) this way AMD tries to compensate the performance loss done by those unfair compilers.
Intel is using much superior instructions and even if AMD is now legally capable (Intel AMD x86 license / AMD Intel x86-64 license ) of using all those instruction, Intel is not letting AMD use the same instruction. << This is the only problem.
People who believe that AMD architecture is worse than Intel are actually wrong. The only main problem (Actually this is not a problem, this is AMD's wish to go more with multithreading ) with the AMD Bulldozer/Piledriver architecture is that a single thread (core) is allowed to utilized only 50% transistor area of a full 4.0 GHz Module, this limits a single thread/core in a bulldozer/piledriver module to theoretically utilize only 2.0 GHz out of 4.0 GHz. This is why current AMD CPUs have bad single thread performance. I've read somewhere this problem is going to be fixed in Steamroller CPUs. But even Steamroller comes with a flawless architecture, it might still be kicked by future Intel Compilers (Only if Intel keeps to do so).
The only thing that hurts me is Intel legally took 64 bit extensions and 128/256 bit FMA3 from AMD and is freely using them with their Haswell CPUs. Ogbviously AMD legally took AVX and other SSE instructions from Intel but AMD can't use it because of Intel's bad strategy.
One more thing, Its very unfair to compare Instructions per cycle (IPC) performance of two different CPU architectures (whether its Intel vs Intel or AMD vs AMD or Intel vs AMD) until the application utilizes same instructions from both competent CPUs.Edited by sumitlian - 7/9/13 at 3:59am