The inclusion of the memory controller in the CPU core represents a major change in the relationship between the motherboard components, as the memory control used to be done by the north bridge of the chipset.
The following diagram shows the classic relationship between a CPU and the memory controller. This example can be a 200MHz FSB Pentium 4 CPU working with a synchronous memory bus.
The clock generator generates a 200MHz clock to the north bridge, this is the FSB. The bus between north bridge and the CPU is 64 bits wide at 200MHz, but four 64 bits packets are sent every clock cycle. This is as if the bus was 4x200MHz and 64 bits wide, this is why the bus speed is often reported as being 800MHz clocked. The memory bus (that links the memory and the controller) is also 200MHz and 64 or 128 bits wide (single or dual channel). As it is DDR memory, two 64/128 bits packs are sent every clock cycle.
The K8 way is quite different.
The clock generator always drives the north bridge, and provides the reference frequency for the HyperTransport link between the north bridge and the CPU. The HyperTransport frequency can so be considered as the FSB, because the CPU uses this frequency to generate its own internal clock, through an internal multiplier.
As shown on the diagram, the memory controller speed is the same than the CPU speed. Memory requests are consequently sent at the CPU speed, on a 64/128 wide bus, according to the number of memory channels. We can see there is no more link between the clock generator and the memory. The memory clock is so obtained from the CPU clock, divided by a factor that depends on the memory specifications. The table below shows the dividers used according to the CPU frequency and the requested memory clock.
Of course, the integrated memory controller does not improve the memory bandwidth, but it allows to drastically reduce the request time. The measured latency is very low, as we'll see further. Moreover, unlike an external memory controller, the performances of the integrated controller of the K8 increase as the CPU speed increase ; consequently, so does the requests speed.
The integrated controller has a particular interest for multi-CPUs systems : in this case, the addressable memory size and the total bandwidth increase with the number of CPUs.
The problem with the integration of the memory controller is the lack of flexibility. The controller is dedicated to a memory technology, and every change in memory standard will need a change in the CPU design. Of course, this does not occur very often (at least not so often as CPU family change), but this could drastically increase the cost of the CPU, as its manufacturation process needs to be changed.
The HyperTransport technology
HyperTransport is a link protocol between CPU and peripherals, and between CPUs themselves in a multi processors system. It allows low latency exchanges, that makes it very relevant for CPUs communications. It uses a 16 bits wide bus at 800MHz, and a double data rate system, that allows it to reach a 3,2GB peak bandwidth.
HyperTransport is planned to be used with the new PCI-X devices.