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Intel to break the 4GHz barrier in 2008 - Page 5

post #41 of 55
Quote:
Originally Posted by Jori View Post
Yeah.. It would be good, but Intel shouldn't promise much until they have throughly broken the 3.0ghz barrier on stock cooling.
Jori, everyone knows that you can take a E6600 to 3.0Ghz on air...

http://www.newegg.com/Product/Produc...82E16819117091
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post #42 of 55
Quote:
Originally Posted by pauldovi View Post
Jori, everyone knows that you can take a E6600 to 3.0Ghz on air...

http://www.newegg.com/Product/Produc...82E16819117091
"Thoroughly" broken the 3.0 barrier.

Thats not 3.0 ghz, thats ranging up into 3.7 or so... I know that they have 3.0 Core 2's but thats also on the server side, the heatsinks are of higher quality in servers.
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post #43 of 55
Quote:
Originally Posted by Jori View Post
"Thoroughly" broken the 3.0 barrier.

Thats not 3.0 ghz, thats ranging up into 3.7 or so... I know that they have 3.0 Core 2's but thats also on the server side, the heatsinks are of higher quality in servers.
You said:

Quote:
Intel shouldn't promise much until they have throughly broken the 3.0ghz barrier on stock cooling.
Throughly means completely...

The Woodcrest breaks the 3.0Ghz barrier and does it on air. You know as well as everyone else that as revisions and steppings mature, the processor speed can increase drastically.
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post #44 of 55
Quote:
Originally Posted by pauldovi View Post
You said:



Throughly means completely...

The Woodcrest breaks the 3.0Ghz barrier and does it on air. You know as well as everyone else that as revisions and steppings mature, the processor speed can increase drastically.
Ehh.. Well I meant into the upper ranges of 3.0, which they are yet to do.
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post #45 of 55
Quote:
Originally Posted by Jori View Post
Ehh.. Well I meant into the upper ranges of 3.0, which they are yet to do.
Any why wouldn't you expect a 45nm chip on a new core revision not be able to break 4.0Ghz?
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post #46 of 55
Quote:
Originally Posted by pauldovi View Post
Any why wouldn't you expect a 45nm chip on a new core revision not be able to break 4.0Ghz?
that it will? Who knows if the next revision will be able to increase the clock speeds dramatically, even on 45nm?

But like I said, it would be good, but Intel shouldnt promise things like that, at least they arnt going for something ridiculous..
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post #47 of 55
Certainly AMD has shown that a die shrink can lead to minimal (if any) overclock gains. Intel has never suffered such an overclock (increased) defeat with a die shrink though so if the past is any indicator of the future, then it quite possibly will extend to a more highly overclockable chip on the 45nm and not to follow AMD's path. Keep in mind that the Prescott (although running hot) still overclocked higher than Northwood.

I certainly hope, at any rate. Releasing a die shrink that does not overclock any better than the previous die is proof of an poor shrink as it shows there is very little technology in the shrink process that deals with leakage, voltage requirements etc. and whose characteristics are usually very indicative of higher overclocking ablility. Even Prescott, with higher leakage than Northwood overclocked higher than Northwood due to the pipeline and lower voltage requirements. Imagine how high Prescott would have clocked if they had dealt with the leakage and thermals?
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post #48 of 55
I thought the high OCs on Intel chips were due to the silicon used ie. the strain on the silicon that allowed for the super high speeds. The SOI silicon that AMD uses doesn't allow for high speeds because it was optimized for minimizing leakage. Intel showed with the P4 architecture that their silicon was able to reach insane clocks. Now they just ported that same high speed silicon over to a much better architecture.
    
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post #49 of 55
Quote:
Originally Posted by Ropey View Post
Even Prescott, with higher leakage than Northwood overclocked higher than Northwood due to the pipeline and lower voltage requirements. Imagine how high Prescott would have clocked if they had dealt with the leakage and thermals?
If they dealt with those Issues, Tejas would probably have been a reality. 5 - 10GHz.
post #50 of 55
Quote:
Originally Posted by Cheetos316 View Post
I thought the high OCs on Intel chips were due to the silicon used ie. the strain on the silicon that allowed for the super high speeds. The SOI silicon that AMD uses doesn't allow for high speeds because it was optimized for minimizing leakage. Intel showed with the P4 architecture that their silicon was able to reach insane clocks. Now they just ported that same high speed silicon over to a much better architecture.
AMD uses Strained Silicon as well, and has been since 90nm.
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