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Weird Musings about TLC NAND

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Since TLC NAND stores 3 bits per cell, why are the dies/packages not a multiple of 3? Even the 840 EVO 750GB uses (4) 128GiB and (4) 64GiB NAND packages.

Another thing, shouldn't alignment also be a multiple of 3?
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Garnet
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post #2 of 2
Quote:
Originally Posted by rui-no-onna View Post

Since TLC NAND stores 3 bits per cell, why are the dies/packages not a multiple of 3? Even the 840 EVO 750GB uses (4) 128GiB and (4) 64GiB NAND packages.

Another thing, shouldn't alignment also be a multiple of 3?

Good questions, given what I have read, it works like this:

The NAND dies and chips (multiple dies on a chip) used on the 840 and 840 EVO are not the same as those used on the 840 Pro. MLC NAND dies are not simply re-purposed into TLC NAND (although it could be.) TLC NAND dies are specific for use as three bits per cell storage.

The confusing part is caused by the assumption that, for example, a 16 GiBit capacity of a TLC NAND die is directly related to the number of transistors/cells in the package, as it has been with SLC and MLC NAND. That is not the case with TLC NAND, the spec is simply the storage capacity of the die.

TLC NAND dies have fewer transistors than SLC/MLC NAND, in order for the die capacity to become a power of two, which is important. A 16 GiBit capacity TLC NAND die actually has 10.7 Gibi transistors/cells. That's why TLC NAND is cheaper, more storage in a smaller die size, and more dies per "wafer", as they are called.

Regarding alignment, we are still working in binary regardless of the number of bits per cell. Also, data is stored in NAND such that the three bits in a TLC cell will never contain bits from the same byte. The same applies to MLC NAND.
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