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Should I worry about PCIe 3.0 for Folding?

post #1 of 5
Thread Starter 
Looking to upgrade my board, and I was wondering should I worry about PCIe 3.0? I have a 7950, and I use it for folding. I plan on adding another card. Would that affect Crossfire at all?
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(9 items)
 
   
CPUMotherboardGraphicsRAM
Xenon Triple Core 3.2 GHz Trinity (Valhalla) ATI Xenos 512 MB GDDR3 @ 700 MHz 
Hard DriveOptical DriveCoolingCooling
250 GB Lite-On DG-16D4S Antec 80mm Tri-Cool SilentX 60mm 
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ASUS VH236 23" 1080p 2ms Generic USB Logitech Keyboard Astro A50 Wireless Headphones 
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post #2 of 5
Hello.
No PCI 3.0 will not make a difference for ether folding or crossfire. Not much of a boost at all.

-ROG
post #3 of 5
I wouldnt worry montney!
post #4 of 5
Thread Starter 
Thanks guys. This will definitely help buying a new board easier! But then what is the point of 3.0?
Main
(9 items)
 
   
CPUMotherboardGraphicsRAM
Xenon Triple Core 3.2 GHz Trinity (Valhalla) ATI Xenos 512 MB GDDR3 @ 700 MHz 
Hard DriveOptical DriveCoolingCooling
250 GB Lite-On DG-16D4S Antec 80mm Tri-Cool SilentX 60mm 
MonitorKeyboardAudio
ASUS VH236 23" 1080p 2ms Generic USB Logitech Keyboard Astro A50 Wireless Headphones 
  hide details  
Reply
Main
(9 items)
 
   
CPUMotherboardGraphicsRAM
Xenon Triple Core 3.2 GHz Trinity (Valhalla) ATI Xenos 512 MB GDDR3 @ 700 MHz 
Hard DriveOptical DriveCoolingCooling
250 GB Lite-On DG-16D4S Antec 80mm Tri-Cool SilentX 60mm 
MonitorKeyboardAudio
ASUS VH236 23" 1080p 2ms Generic USB Logitech Keyboard Astro A50 Wireless Headphones 
  hide details  
Reply
post #5 of 5
PCIe 3.0 upgrades the encoding scheme to 128b/130b from the previous 8b/10b, reducing the overhead to approximately 1.54% ((130-128)/130), as opposed to the 20% of PCIe 2.0. This is achieved by a technique called "scrambling" that applies a known binary polynomial to a data stream in a feedback topology. Because the scrambling polynomial is known, the data can be recovered by running it through a feedback topology using the inverse polynomial.[28] PCIe 3.0's 8 GT/s bit rate effectively delivers 985 MB/s per lane, double PCIe 2.0 bandwidth. PCI-SIG expects the PCIe 3.0 specifications to undergo rigorous technical vetting and validation before being released to the industry. This process, which was followed in the development of prior generations of the PCIe Base and various form factor specifications, includes the corroboration of the final electrical parameters with data derived from test silicon and other simulations conducted by multiple members of the PCI-SIG.



-ROG
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