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Is this possible? Here's what I've tried.

post #1 of 2
Thread Starter 
A little background:
I've had on old macbook(3.1) sitting around for ages now, with a faulty LCD, keyboard, and battery that don't work. And what's more, I've long since cannibalized the hard drive to use as my portable drive.
Recently I decided I wanted to try to resurrect it again with another 100gig hard drive I had come into. But with no installation discs in sight, I decided to turn to Ubuntu. 12.04 did not run very well and I eventually switched to 10.04, seems to work much better.

I've been using it to run Project64 and Dolphin, and It has been equipped with a ridiculous cooling system I had laying around in order to do this(as I found core timing issues in project64 at higher temperatures). Dolphin runs just barely, and I'd like to be able to run it closer to Gamecube speeds. I figure I don't really care about this laptop anymore, and since I've already stuck this giant heatsink and fan on it:



I might as well try to overclock it. I'm prepared to face the consequences.

Here's some more details on the system:
Intel Core 2 Duo T7500 CPU @2.20GHZ(x2)
1g RAM
Ubuntu 10.04 on kernel 2.6.32-38-generic


I should probably start off by saying I'm no computer expert by any means, and I'm even more shaky with linux(my only other experience with it being modding my PSP a few years ago) so don't get too angry if i'm completely wrong about a lot of things. I'd appreciate the corrections.

Now, I'm aware of the fact that Macs don't have a BIOS that you can boot into, but instead an EFI firmware that jumps into your OS. If anyone has more details on this, I would love to hear them. As far as I know there is no direct way to alter this in any way. I hypothesize that you would have to write your own custom EFI firmware(if this can even be done?) which is clearly way over my head. From scouring google, I did see a few people on some forums mention that It might be possible to alter your system's CPU frequency by altering the FSB value using some sort of software. And having seen this:
http://www.overclock.net/t/1205257/overclock-cpu-in-linux-necessary-program-names-given
It seems like c2ctl is my best(if only) bet.

So I ran
Code:
sudo modprobe msr
to get the msr to show up in /dev/cpu/*/,
If you look at the c2ctl readme (available on the website http://www.ztex.de/misc/c2ctl.e.html) it says that you need write access to the msr files in the cpu directories. They can't be read by any Ubuntu software, and when I try to execute ./msr I get permission denied. I later found out that they can only be read and written in 8 bit words using rdmsr and wrmsr. so I can do that. Cool. These little letters and numbers mean nothing to me, but at least I can read(and presumably write) them. I guess c2ctl will be doing that. So when I run c2ctl and look at the cpu info, I'm told that both cpus have fid=6 and vid=23. great. So I want to try fid=8 and vid=32. Now before then I calculated using the provided formula(uCPU=800mV*vid+12.5mV) that I would need a vid of 16 in order to properly undervolt the CPU according to this guide: [URL]=http://www.overclock.net/t/308654/undervolt-laptop-guide-intel-c2d-t7500[/URL] based on the substitution (uCPU-800)/12.5=vid. But since this number is below the minimum voltage that c2ctl read out, I decided to go with the vid given in the readme. so my command was
Code:
./c2ctl 0-1 8 32
c2ctl simply changed the target voltage, but the current voltage remained the same.
Is this due to the ESIT? I have read that you are still able to overclock with it enabled, but I still don't have a very solid idea of how it works.
Anyway, it would appear that in order for c2ctl to work, you may have to amend the dsdt of your system so that it believes that it can actually reach these attributes. So I got c2ctl to spit out the dsdt templates for the cpus(just one shown):
Code:
{
            Name (_PPC, 0x00)

            Name (_PCT, Package (0x02)
            {
                ResourceTemplate ()
                {
                    Register (FFixedHW, // PERF_CTL
                        0x10,              // Bit Width
                        0x00,               // Bit Offset
                        0x00000199 // Address
                        ,)
                },

                ResourceTemplate ()
                {
                    Register (FFixedHW, // PERF_STATUS
                        0x10,               // Bit Width
                        0x00,    // Bit Offset
                        0x00000198, // Address
                        ,)
                }
            })

            Name (_PSS, Package (0x01)
            {
                Package (0x06)
                {
                    3000, // f in MHz
                    75000, // P in mW
                    10, // Transition latency in us
                    10, // Bus Master latency in us
                    0x0000880F // value written to PERF_CTL; fid=6, vid=23
                    0x0000880F // value of PERF_STATE after successful transition; fid=6, vid=23
                }
            })
}

So, here's where I do something I am about 90% sure is wrong. The readme for c2ctl says that there should be a clause for every p-state and respective information, but I just figured to test I would enter the only p-state to be fid=8 vid=23, and i entered the info solely based on what the example dsdt in the tutorial had on it. Like so:
Code:
Name (_PSS, Package (0x03)
        {
            Package (0x06)// P-State 0
            {
                3104, // f in MHz
                75000, // P in mW
                10, // Transition latency in us
                10, // Bus Master latency in us
                0x00000820, // value written to PERF_CTL; fid=8, vid=32
                0x00000820// value of PERF_STATE after successful transition; fid=8, vid=32
            },
Next came the task of amending my system's dsdt. Apparently you can install iASL to disassemble and recompile your dsdt. So that's what I did.
First I dissasembled and then recompiled to see if there were any existing errors in my dsdt.
Code:
sudo iasl -d dsdt.dat
sudo iasl -tc dsdt.dsl
There were none. Next I decided to try to add in my changes. So i brought up my dsdt.dsl in gedit. Before editing, the cpu section(found with ctl+f) looked like this:
Code:
Scope (\_PR)
    {
        Processor (CPU0, 0x00, 0x00000410, 0x06) {}
        Processor (CPU1, 0x01, 0x00000410, 0x06) {}
    }
And with my changes:
Code:
Scope (\_PR)
    {
        Processor (CPU0, 0x00, 0x00000410, 0x06) {
            Name (_PPC, 0x00)

            Name (_PCT, Package (0x02)
            {
                ResourceTemplate ()
                {
                    Register (FFixedHW, // PERF_CTL
                        0x10,              // Bit Width
                        0x00,               // Bit Offset
                        0x00000199 // Address
                        ,)
                },

                ResourceTemplate ()
                {
                    Register (FFixedHW, // PERF_STATUS
                        0x10,               // Bit Width
                        0x00,    // Bit Offset
                        0x00000198, // Address
                        ,)
                }
            })

            Name (_PSS, Package (0x01)
            {
                Package (0x06)
               {
                3104, // f in MHz
                75000, // P in mW
                10, // Transition latency in us
                10, // Bus Master latency in us
                0x00000820, // value written to PERF_CTL; fid=8, vid=32
                0x00000820// value of PERF_STATE after successful transition; fid=8, vid=32
            }
            })
 }
        Processor (CPU1, 0x01, 0x00000410, 0x06) {
            Name (_PPC, 0x00)

            Name (_PCT, Package (0x02)
            {
                ResourceTemplate ()
                {
                    Register (FFixedHW, // PERF_CTL
                        0x10,              // Bit Width
                        0x00,               // Bit Offset
                        0x00000199 // Address
                        ,)
                },

                ResourceTemplate ()
                {
                    Register (FFixedHW, // PERF_STATUS
                        0x10,               // Bit Width
                        0x00,    // Bit Offset
                        0x00000198, // Address
                        ,)
                }
            })

            Name (_PSS, Package (0x01)
            {
                Package (0x06)
               {
                3104, // f in MHz
                75000, // P in mW
                10, // Transition latency in us
                10, // Bus Master latency in us
                0x00000820, // value written to PERF_CTL; fid=8, vid=32
                0x00000820// value of PERF_STATE after successful transition; fid=8, vid=32
            }
            })
 }
Once again, I have no idea about coding or anything. So if this is blatantly wrong, please let me know.
I recompiled it with no errors.
Next comes the hard part. How do I get my computer to read this thing?
Apparently the best way is to build a new kernel from the source, while telling it to use your custom dsdt.
so using these guides:
http://vatriani.wordpress.com/2010/07/18/dsdt-fix-fsc-amilo-xi-1526/
(don't speak german, had to use google translate)
http://ubuntuforums.org/showthread.php?t=1341580
http://blog.avirtualhome.com/how-to-compile-a-ubuntu-lucid-kernel/
I retrieved a kernel source(2.6.32-38) and used make xconfig to set it to use my custom dsdt. I managed to compile and install my kernel, and select it from the grub bootloader. The only noticable difference between it and my other kernel is that I get a warning from cpu frequency scaling monitor that says “CPU frequency scaling unsupported”. The monitor is just constantly at 2.19 now. When I try to use c2ctl, I am presented with the same problem: I can set the target fid and vid, but the current values never change.
In this kernel, I decided to disassemble the dsdt and see if my custom version was used.
It is definitely different from before, but the vital clause where my changes were made is gone now.
here's what the cpu section of the new dsdt looks like:
Code:
Scope (_PR)
    {
        Processor (CPU0, 0x00, 0x00000000, 0x06)
        {
            Name (_PPC, Zero)
            Name (_PCT, Package (0x02)
            {
                ResourceTemplate ()
                {
                    Register (FFixedHW, 
                        0x10,               // Bit Width
                        0x00,               // Bit Offset
                        0x0000000000000199, // Address
                        ,)
                }, 

                ResourceTemplate ()
                {
                    Register (FFixedHW, 
                        0x10,               // Bit Width
                        0x00,               // Bit Offset
                        0x0000000000000198, // Address
                        ,)
                }
            })
            Name (_PSS, Package (0x01)
            {
                Package (0x06)
                {
                    0x0C20, 
                    0x000124F8, 
                    0x0A, 
                    0x0A, 
                    0x0820, 
                    0x0820
                }
            })
        }

        Processor (CPU1, 0x01, 0x00000000, 0x06)
        {
            Name (_PPC, Zero)
            Name (_PCT, Package (0x02)
            {
                ResourceTemplate ()
                {
                    Register (FFixedHW, 
                        0x10,               // Bit Width
                        0x00,               // Bit Offset
                        0x0000000000000199, // Address
                        ,)
                }, 

                ResourceTemplate ()
                {
                    Register (FFixedHW, 
                        0x10,               // Bit Width
                        0x00,               // Bit Offset
                        0x0000000000000198, // Address
                        ,)
                }
            })

So I guess my question is, why? At this point I am assuming that the alterations to the dsdt are what I need to be doing. But once again, if I'm just completely off in the wrong direction, let me know. It is worth mentioning that the c2ctl readme also states that the core voltage must be able to be set by the CPU. This was something I was unable to determine.

Well, sorry for the long post! This is my first time trying anything so in-depth, so I'm eager for feedback.
post #2 of 2
If the original data is suppose to be written to 0x0000880F why did you use 0x00000820 from the example? I'm guessing this is suppose to be a register where the data is suppose to be written from the variables "fid" and "vid" into PERF_CTL which seems to be referenced as FFixedHW. I have no idea what Bit Width/Offset are actually for. I only know a little assembly haven't really dug deep enough so don't expect me to be an expert.

Also this is confusing:
Code:
Scope (\_PR)
    {
        Processor (CPU0, 0x00, 0x00000410, 0x06) {}
        Processor (CPU1, 0x01, 0x00000410, 0x06) {}
    }

Why would you add this code into into the DSDT template generated from c2ctl? From the looks it looks like they're some kind of CPU registers. Not quite sure what they do, the only thing I can guess is 0x00 and 0x01 is the CPU number, unsure what 410 and 06 codes are.

As for this code:
Code:
Name (_PSS, Package (0x01)
            {
                Package (0x06)
                {
                    3000, // f in MHz
                    75000, // P in mW
                    10, // Transition latency in us
                    10, // Bus Master latency in us
                    0x0000880F // value written to PERF_CTL; fid=6, vid=23
                    0x0000880F // value of PERF_STATE after successful transition; 
                    fid=6, vid=23
                }
            })

The only thing I can guess from the comments is that the 3,000 is the frequency at which the CPU runs and the 75,000 is the measurement in milliwatts converted to watts is 75 Watts of power. I'm not an engineer so I don't know what those transition and bus master latency actually do. But it looks possible that it only holds the voltage value in 0x0000880F if it successfully switched to it without crashing? By the way those double slashes // that you see are just C++ style comments so anything after them do not affect anyway the code is compiled.

I have no idea what this piece of code is:
Code:
Name (_PPC, 0x00)

            Name (_PCT, Package (0x02)
            {
                ResourceTemplate ()
                {
                    Register (FFixedHW, // PERF_CTL
                        0x10,              // Bit Width
                        0x00,               // Bit Offset
                        0x00000199 // Address
                        ,)
                },

PPC = Power PC Architecture? But that doesn't make sense since Apple switched to Intel CPU's a while ago. I think you may need to read c2ctl p-states again, p-state=power state? That's all I can really help you with. You'd probably have more luck posting this in the programming section as there are much more experienced programmers than me.
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Skylake Is Here!
(17 items)
 
  
CPUMotherboardGraphicsRAM
Intel i7 6700K Batch #L535B021 4.7Ghz @ 1.296V GIGABYTE G1 Gaming GA-Z170X-Gaming 7 EVGA Geforce GTX 970 SSC ACX 2.0+ G.SKILL TridentZ 16GB DDR4 3000 
Hard DriveHard DriveHard DriveCooling
Samsung 950 Pro M.2 512GB  Crucial BX100 250 GB SanDisk SSDPlus 240 GB NZXT Kraken X61  
OSMonitorKeyboardPower
Windows 8.1 & 10 Dell UltraSharp 2913WM 21:9 2560x1080 Ducky Shine 4, CODE WASD, Deck Legend, G710+ EVGA SuperNova G2 850W 
CaseMouseMouse PadAudio
Phanteks Enthoo Evolv ATX Mid-Tower Ducky Secret SteelSeries Fostex Purple Heart TH-X00 
Audio
AKG K553 Pro, Philips SHP9500, Superlux 668B, S... 
  hide details  
Reply
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