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E6400 vs E6600 - Page 4

post #31 of 32
Sorry Val, but Wiki is not a reliable source, I could edit that myself and so far I'm yet to see a valid proof report stating that Allendales have a 2MB of L2 cache disabled.

Kinda funny to think that Intel would waste money putting full 4MB of cache but they'll disabled 2MB. This is not HTT where HTT was an extension to the architecture, this is s physical part which cost money and I don't know about you guys but putting something means it cost something and if it's not going to be used, then it goes to waste.

Is Intel wasting money? I don't think so. I wonder if my Northwood 3.0ghz had a L3 cache disabled, since that the original Extreme Editions CPUs had up to L3 cache, but I don't think so.
post #32 of 32
Well if the architecture is sufficiently modular they could make it so they have the cache in 4 1MB chunks, 2 chunks per core. If there is a serious flaw in only ONE of the cache chunks they could disable a chunk on the other core as well and still be able to sell a 'faulty' chip that other wise works fine. Makes more financial sense than you think if that be the case in the architecture.
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