Yeah please cool out guys. It would be fairly embarassing at this point to get our main Kaveri thread closed and locked before the chip is even released.
Originally Posted by SpeedyVT
Or perhaps L3 is dated to their architecture and using it only creates problematic loop backs that may have improved IPC in previous core to core designs but not in one where two cores already share the L2 cache.
I think this is most likely the case. Honestly though, we shouldn't even be arguing about this as One, it's an engineering sample and a mobile part to boot things could still be turned off or buggy and Two, Floating point stuff is very likely going to be handled by the GPU portion of the chip, giving us no idea beyond theoretical claims of it's actual performance.Edited by yawa - 11/16/13 at 9:16pm