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The FrontSide Bus and Data Bandwidth

post #1 of 3
Thread Starter 
This is not a question related thread. I have decided that we need to make the community more aware of these terms, and how they are derived.

The FrontSide Bus

Members of the community will know the term FSB (FrontSide Bus). This term is rather old, coming from around the early Pentium 3 period.

The FrontSide Bus, as we know it, is the data channel that connects the processor to the components outside of it's on die structure. We know this communication line as the FrontSide Bus.

For your own information the FrontSide Bus no longer exists, even though we still call the communication channel the FSB.

In the early Pentium 3 era the chips contained high speed memory cache in the processor package. To communicate with these chips a bus system called the BackSide Bus was created. This bus allowed communication between the processor and the Cache Memory. Therefore the connection to the outer components off die was classed as the FrontSide Bus.

Now as cache is directly implemented onto the processor die these terms no longer exist, technically. The Term FSB does not exist, as a hardware connection to the outside world, as there is a singular bus system to accomplish that.

Of course we still use the term, even though it’s now longer within Micro-Processor design.

Now, onto Data Bandwidth.

I will show you how to calculate the bandwidth of processors manually, without having to resort to technical documentation

Example: Intel Pentium 4 540J.
Clock Speed = ~3200MHz
QDR Bus: ~800MHz
Bus Clock: ~200MHz

In our example we are using a processor that is capable of a maximum of four data transfers per clock cycle.

Please Note: Not all processors will use a "Four Data Transfers per Clock Cycle" system. The old Athlon XP only used a dual (2) system.

First we will need to calculate the Transfers per Second value.
This is calculated by multiplying the Bus Clock by the Transfers per Clock Cycle.

Value = 200 x 4 = 800MHz.

This is how you calculate the QDR value of 800MHz.
The Quad Pumped FSB states that four transfers per clock cycle can be accomplished. The bus speed runs at 200MHz, but can act as 800MHz due to the ability to transfer more than one data transfer per clock cycle (maximum of four).

Now that we have the Maximum Transfers per Second value (MT/s) we can calculate the Max data bandwidth of the Micro-Processor.

To calculate this value you multiply the Transfers per Second value by the Integer Eight (8). This counts as the amount of "bits" per data cycle.

Therefore to calculate the Maximum Data bandwidth for this processor:

800 x 8 = 6400MB/s.

In reality these values may be unattainable. Granted these values can be ascertained by the Micro-Processor, but don't forget the Main Memory has a part to play in the Data Bandwidth

Hope this clears a few things up
post #2 of 3
Very informative post, very complete and very helpful. Thanks for taking the time to make this!

+ Cookie, as I can't +REP you.
The Shehanigator
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post #3 of 3
Very nice write-up...I think this will help to correct any misnomers or mis-associations with terms
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