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[Official] Asus Rampage IV Black Edition Owners Club! - Page 653

post #6521 of 14763
Quote:
Originally Posted by tistou77 View Post

To me (bios 0602) smile.gif



CPU Multi is x36 but Aida64 show 34...

nice bandwidth:thumb:thumb.gif
post #6522 of 14763
Hello - back again! smile.gif

For months ago i bought the Black, but with my Kingston HyperX DIMM XMP Kit 64GB, DDR3-1600, CL9 (KHX16C9K8/64X) doesn't work with this Board,
i tested also 2 different G.Skill Kit's DDR3-1600 CL9 & CL10 (each 32gb).
They doesn't work too...

So my questions:

I had every time reboots with these kits of memory

was that a memory problem ?

or was it a Black problem- was my board faulty ?


I maybe want to order the Black again, maybe with memory whitch is in the QVL list like this kit:

G.Skill RipJawsZ DIMM Kit 64GB, DDR3-2400, CL10-12-12-31 (F3-19200CL10Q2-64GBZHD)

Does someone run 64GB with this board !?

Now I own a 4960X but in the past i already own this 64GB G.Skill Kit - but i never got the DDR3-2400 CL10 stable (this was on the normal REIV with a 3960X CPU).


Thank you very much!
post #6523 of 14763
At least you got an explanation above I suppose. That string is not far off what you guys need to know about OCP. If one really has a keen interest in electronics - it would be a good idea to take a course. The fundamentals is all one needs for most stuff - to get by.
post #6524 of 14763
Looks like I might have picked up a good chip to go along with this board.

This is with + .010 offset, 1.125 vtt and vccsa, high llc.

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Fused III
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post #6525 of 14763
Quote:
Originally Posted by Raja@ASUS View Post

I think some people are confused about what OCP is.

Think of OCP like a re-settable fuse. If you use a bigger fuse it will simply pass more current before it trips. Under normal operation, the current is not forced into the CPU; the CPU draws what it needs. For instance, if OCP is set to a value that shuts off at 120amps, but the CPU needs 140 amps, the VRM will shutdown as soon as the current draw exceeds 120 amps for more than a few micro-seconds. The higher you set the OCP the more current the VRM can supply the CPU if the CPU needs it.


So why have OCP at all? OCP is in place to prevent the VRM from supplying all of its current in a fault event. Just as fuses break a circuit. There are instances where one could set a threshold to prevent "more" damage. It won't stop the CPU from dying if something goes short in the die, but it may stop the board traces or related VRM components from burning up due to an open load.

Red at 140% is actually default on Auto BTW.

-Raja

I recall that OCP setting is ONLY marked with red when it's set to 140% in previous R4BE and R4E build.
However, this setting is now red for all values that exceed 140%. What does this mean? Raja, I think you didn't explain why they are marked with red in your last reply. My interpretation is that ASUS is emphasizing that this setting is potentially dangerous when it exceeds 140% and alerting people to pay attention to it.
post #6526 of 14763
Quote:
Originally Posted by Raja@ASUS View Post

At least you got an explanation above I suppose. That string is not far off what you guys need to know about OCP. If one really has a keen interest in electronics - it would be a good idea to take a course. The fundamentals is all one needs for most stuff - to get by.

That is just an example. If you look at help strings in DRAM setting, you will find that they're totally useless.wink.gif
One more quick question for you, Raja, why I can't set T_CCD to 0 for 2666CL10-12-12-26-1T. It causes instantly shut-down or BSOD when I run P95 V28.3 customized test burning 90% RAM. Kit is Corsair quad channel kit with Sammy IC. I tried increase DRAM, VTT, VCCSA, Vcore volt, set VCCSA LLC to different values. Still instant BSOD. Also, why the changes in VTTDDR volt setting is ignored. Manually set to 0.85 in BIOS but it's actually 0.75 when check in Windows using Turbo Vcore.
Does T_CCD have great impact to overall performance, what I can see from AIDA64 bandwidth tests, it seems impact is quite big.
Edited by asfgbdnf - 3/15/14 at 7:44am
post #6527 of 14763
The red levels are now simply higher than you should need for 24/7 OC as the current sensing has been shifted.. AS for the "danger", I think that's quite clear in the post I wrote about OCP above.


DRAM - that subject is so complex there is no way to break it down easily. EE level stuff a lot of it .
Edited by Raja@ASUS - 3/15/14 at 7:36am
post #6528 of 14763
*edit*
post #6529 of 14763
Ideally one should leave tCCD at 0 or 4 (both the same thing). Back to back reads (and writes) are where sustained DRAM read and write performance comes from. After a row is latched all consecutive data can be taken from the row by spacing each DRAM burst at 4 clock intervals. Therefore if you set 5, after each burst, there will be a 1 clock wait before the next 4 clock burst. If you set 6 then there will be a 2 clock wait between each burst - and so on the higher you go.

On these architectures data is not fragmented like it used to be on platforms several years ago (thats why the primary timings make less difference to performance now). Hence, keeping tCCD at it's minimum spacing is a good idea.


If one is just chasing the raw bandwidth for validation, that is another matter.
Edited by Raja@ASUS - 3/15/14 at 7:58am
post #6530 of 14763
Did we ever find out if there is a difference between 0601 & 0602?
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