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[Official] Asus Rampage IV Black Edition Owners Club! - Page 654

post #6531 of 14746
Quote:
Originally Posted by Raja@ASUS View Post

Ideally one should leave tCCD at 0 or 4 (both the same thing). Back to back reads (and writes) are where sustained DRAM read and write performance comes from. After a row is latched all consecutive data can be taken from the row by spacing each DRAM burst at 4 clock intervals. Therefore if you set 5, after each burst, there will be a 1 clock wait before the next 4 clock burst. If you set 6 then there will be a 2 clock wait between each burst - and so on the higher you go.

On these architectures data is not fragmented like it used to be on platforms several years ago (thats why the primary timings make less difference to performance now). Hence, keeping tCCD at it's minimum spacing is a good idea.


If one is just chasing the raw bandwidth for validation, that is another matter.

Please clarify one thing, you said 'leave tCCD at 0 or 4 (both the same thing)'. I guess, here '0' is the value we use for settings in BIOS and '4' is measure of the actual DRAM clocks, in other words, set tccd to 0 means spacing each DRAM burst at 4 clock intervals. So actually the waiting time between each burst is the value we use in BIOS setting plus 4 clocks.
If set tccd to 4, the waiting time is 8 clocks in practice, am I right?
Also, could you please explain the VTTDDR problem?
post #6532 of 14746
1) In the past 0 disabled the offset logic (minimum spacing) while 2&3 revert to 4 internally. Chances are it's still the same unless Intel decided to change things, you can test this easily enough by setting 0 then 4 and seeing if there is any change. In fact most of the third timings are bound by a 4 clock minimum spacing as well internally. it just depends if Intel decide to apply offsets to the minimum spacing or leave the "impossible" register bits open and revert them (a few of the third timings are offsets of auto sensed values I think).

DRAM timing law is what it is though - 4 clocks is the burst length and that spacing needs to be observed at the chipset level.


2) Might be a bug with TurboV. On this platform VTTDDR is probably best left at 50% of VDD (VDIMM) which is what Auto is.

-Raja
Edited by Raja@ASUS - 3/15/14 at 8:30am
post #6533 of 14746
Quote:
Originally Posted by skupples View Post

Did we ever find out if there is a difference between 0601 & 0602?


0601 was the 125 strap patch for CPU ratios over 36 only. 0602 = 0601 + current sensing patch. That's all.
Edited by Raja@ASUS - 3/15/14 at 8:37am
post #6534 of 14746
Thx Raja.
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post #6535 of 14746
Quote:
Originally Posted by Raja@ASUS View Post


2) Might be a bug with TurboV. On this platform VTTDDR is probably best left at 50% of VDD (VDIMM) which is what Auto is.

-Raja

Thanks for your explanation. This problem exists back to R4E and it seems it's still unfixed in R4BE.
post #6536 of 14746
Quote:
Originally Posted by Raja@ASUS View Post

0601 was the 125 strap patch for CPU ratios over 36 only. 0602 = 0601 + current sensing patch. That's all.

What is the problem under 125 strap ? I didn't notice any problem.
post #6537 of 14746
Quote:
Originally Posted by asfgbdnf View Post

What is the problem under 125 strap ? I didn't notice any problem.

some sandy-bridge CPUs were not working with strap 125. Issue has been resolved in the 0601, i can attest to the fix working.
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post #6538 of 14746
well this thread blew up after raja started answering questions lol biggrin.gif

Glad to have more reps on here helping us out, Thanks Raja!
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post #6539 of 14746
As you can clearly see there is a lot of unanswered questions regarding this motherboard and its settings!!

Sorry Raja to ask you so many as i understand your busy with projects to do, but we all just wish to run this motherboard to its best ability.

In a relatively safe manner whether overclocking to its Max or for everyday use, as for my questions to you i was just checking my own ideas here.


Respectfully,

AJ.
post #6540 of 14746
Quote:
Originally Posted by Raja@ASUS View Post

As said above 0602 patches current sensing so high levels of OCP do not need to be set.

I don't agree. At stock, new board will still shut down @ stock, listing PSU instability as cause of shutdown on POST.


But OC, or adjust current limits, it's fine.

I see board defaults to 140% under auto, too. Perhaps it's that setting screwing with me?


Honestlyy, Raja, I want to run normal stock. OC is great with this board/BIOS, but stock is not stable at all, and it's all about VRM settings under auto rules. Manually setting to "stock" values makes it even worse.


So, what you are telling me is that my CPU is the fault here, right?

And that each user, when running into this, will have to find out what each CPU requires, correct?
Quote:
Originally Posted by asfgbdnf View Post

What is the problem under 125 strap ? I didn't notice any problem.

There are at least 3 different version of SB-E chips ; C0, C1, and C2. Not all versions had problems with 125 BLCK, and some chips that are a bit poopier than others had issues that were not present on other boards. This is now fixed that I can tell.

But I cannot get proper PCIe slot function still with C1 ES.
Edited by cadaveca - 3/15/14 at 1:08pm
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