Originally Posted by Blameless
We have had 128-bit instructions on x86 since at least SSE (Pentium III), and AVX2 instructions are 512-bit.
What we don't need are 128-bit general purpose registers or memory addressing.
This. Purpose-built instructions can take advantage of the large datasets passed to them, general purpose registers, memory addressing and ALU ops would benefit less than the overhead it would add by moving to 128bit or higher.
Originally Posted by sumitlian
I've read somewhere AVX2 can split four 256 bit micro operations, all in one cycle, it means it can do 1024 bit. But cache bus width is limited to 512 bit, this violates the optimum efficiency for one cycle. Upcoming AVX3.2 might fully support it.
What I don't fully understand that what type of application 1024 bit instruction can be applied for ?
Graphics acceleration benefits largely from the larger operations. So do things where you are mapping 64 or 128 bit calls between two architectures (VM's, emulation, dynarec) Furthermore, scientific purposes would probably see large performance gains with 1024-bit instructions. Just a few things I can think of off the top of my head.