I like the structuring of you're article. However there are a magnitude of errors within it
Slight misconseption. Mega states to the Power positive Nine. Therefore the actual cycles accomplished are 800x10^9.
800 Hertz (Cycles Per Second) would give you 800 cycles
This throws you're entire point about the latency's just about out of the window from here on, as they are extremely small.
Technically the principle is correct, yes. However the bandwidth is actually 8528MB/s. This will therefore limit the Memory Data Transfer TO THE CPU
to this value. This does not necessarily mean the Memory is limited to this data flow to other components (i.e. In-Direct Transfer to GDR).
The latency timing between the system can not just be stated that simply.
DRAM chips contain grids of memory cells arranged into Rows and Columns. I will skip the workings of memory and go straight onto the latency part.
RAS = Row Access Strobe. This has a latency obviously. It's prime role is to tell the DRAM whether an address is being supplied for a Row.
CAS = Column Access Strobe = Same, but for Columns (More important than RAS).
When a new Row is accessed there will be a RAS to CAS delay. The CAS latency comes next, followed by the Row Precharge, and then continue.
So 800x10^9 cycles = 800000000000 Clock Cycles.
Latency = 5-5-5-10 = 25 cycles?
Not a problem for that latency I think