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[GN] AMD: "FX is Not EOL" & Why What We Need in a CPU is Changing - Page 18

post #171 of 200
Regardless of where this idea (SMT-like for AMD) comes from ,AMD is facing a challenge with CMT "logistics". We can sit and pretend there is nothing wrong with their arch but a big part of their recent misfortune is CMT's size/power consumption/performance. Even if they remain 1M/2C/2T, by simply adding hardware to their design, their processors effectively become full cores. While this isn't something particularly bad ,it flat out cancells the idea behind CMT. A 2M/4C/4T excavator would trail cpu-wise a haswell/broadwell i5 pretty much everywhere. A theoretical 3M/6C/6T would beat that i5 in MT but trail a hyperthreaded quad i7 in single and most MT workloads alike. While some of you would find this scenario appealing, all I see is the 2009-2010 story happening again. Phenom II X4 losing vs i5 and Phenom II X6 losing vs i7 and AMD forced to sell bigger dies for less in laptops. If this was/is their ambition, they would have been better off designing a new full core from scratch instead of going CMT only to make a full circle. Or just take their little core and slightly modify it then upscale it.

One FPU shared between two threads? Isn't that supposed to be happening for bulldozer family only with AVX workloads, when the 128-bit independent units are "merged" into a single 256-bit one (effectively making it a quad) while for all other purposes the design is true 8 core when it comes to floating point?

http://en.wikipedia.org/wiki/Bulldozer_%28microarchitecture%29

"Two symmetrical 128-bit FMAC (fused multiply–add capability) floating-point pipelines per module that can be unified into one large 256-bit-wide unit if one of the integer cores dispatches AVX instruction and two symmetrical x87/MMX/SSE capable FPPs for backward compatibility with SSE2 non-optimized software"

There is nothing fundamentaly wrong with multiple threads per core. IBM is doing it, intel is doing it, AMD can do that as well. It is the way you design and execute it that matters.The main thing AMD has to do this time is guarantee that windows will deal with the extra threads properly and hopefully the extra hardware they seem to be using will work its magic.
Edited by Kuivamaa - 12/12/13 at 5:48am
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post #172 of 200
I'd be willing to adopt APU if APU's were ready for enthusiast use, which currently they aren't. How they become ready, I really don't care, it just needs to happen.kA7FwG
post #173 of 200
I'm saying doing SMT within each integer core will reduce the single threaded performance of the core - this is almost certain. It might get you some more multithreaded throughput, but its not worth the single threaded loss. Its good that the marketing dept. will be able to advertise "8 threads!" but otherwise a bad idea. If you want more multithreaded performance, then add another module - 6 INT cores with high IPC should be more than enough to match 4 cores with HT.

SMT only seems to work well on RISC arches like POWER or Itanium. On x86, both AMD and intel stick to 2 threads per core (or module in AMD's case) for a reason.

Edit:
Also to the point about the FPU, yes it's shared by two threads currently. When one thread is using the FPU all resources can be consumed. When two threads are using it, resources must be shared fairly but also try to ensure the best throughput possible for each thread. This is how scheduling can become extremely complicated due to the varying instruction latencies of x86 instructions. Share an FPU between 4 threads and its a nightmare.

4 ALU/AGU per core and 4x128bit FMACs shared between two cores is likely what we're looking at for Excavator.
Quote:
Originally Posted by Kuivamaa View Post

Regardless of where this idea (SMT-like for AMD) comes from ,AMD is facing a challenge with CMT "logistics". We can sit and pretend there is nothing wrong with their arch but a big part of their recent misfortune is CMT's size/power consumption/performance. Even if they remain 1M/2C/2T, by simply adding hardware to their design, their processors effectively become full cores. While this isn't something particularly bad ,it flat out cancells the idea behind CMT. A 2M/4C/4T excavator would trail cpu-wise a haswell/broadwell i5 pretty much everywhere. A theoretical 3M/6C/6T would beat that i5 in MT but trail a hyperthreaded quad i7 in single and most MT workloads alike. While some of you would find this scenario appealing, all I see is the 2009-2010 story happening again. Phenom II X4 losing vs i5 and Phenom II X6 losing vs i7 and AMD forced to sell bigger dies for less in laptops. If this was/is their ambition, they would have been better off designing a new full core from scratch instead of going CMT only to make a full circle. Or just take their little core and slightly modify it then upscale it.

One FPU shared between two threads? Isn't that supposed to be happening for bulldozer family only with AVX workloads, when the 128-bit independent units are "merged" into a single 256-bit one (effectively making it a quad) while for all other purposes the design is true 8 core when it comes to floating point?

http://en.wikipedia.org/wiki/Bulldozer_%28microarchitecture%29

"Two symmetrical 128-bit FMAC (fused multiply–add capability) floating-point pipelines per module that can be unified into one large 256-bit-wide unit if one of the integer cores dispatches AVX instruction and two symmetrical x87/MMX/SSE capable FPPs for backward compatibility with SSE2 non-optimized software"

There is nothing fundamentaly wrong with multiple threads per core. IBM is doing it, intel is doing it, AMD can do that as well. It is the way you design and execute it that matters.The main thing AMD has to do this time is guarantee that windows will deal with the extra threads properly and hopefully the extra hardware they seem to be using will work its magic.

Edited by MrJava - 12/12/13 at 8:17am
post #174 of 200
post #175 of 200
Quote:
Did they just get all fierce after beating low power desktop parts based on dog dodo.
Well usually when AMD is fierce about something they perform but if something is really really hyped by employees it is most likely a fail.
post #176 of 200
AMD of today is pretty different, lots of different people in the company. Marketing guys still troll, but not nearly as much as they used to in the Dirk Meyer/Hector Ruiz era. AMD of today don't even talk about their products outside of these presentations every now and then, which leaves us speculating our asses off on every little morsel we can get our hands on. devil.gif
post #177 of 200
Sweclockers are often well informed. Unsurprisingly, Kabini has the central role on these slides, further indicating AMD is focusing mostly on little core.
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post #178 of 200
I'd wager that AMD is going to be focusing on Kaveri publicly either way, it's their next release after all.

Plus, if they are waiting for a new node to do AM4 or whatever it's entirely possible they don't want to give a guessed release date as they may not really know well enough...We don't want another BD in terms of delays.
    
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post #179 of 200
Quote:

Of course it was real.

As I said, denying the authenticity of the roadmap was just some random PR from the guy over at AMD. They're under NDA most likely so it's not like they can say that they've seen it etc.
 
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post #180 of 200
One thing that i dont understand. WHY leaving "big core" after they did +30% IPC perfromance with steamroller?
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