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Are intel chips and amd chips RISC

post #1 of 12
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^^ is it?
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post #2 of 12
Not any of the current architectures. There are some historical ones from both Intel and AMD, but nothing current. Look here for more info.
    
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post #3 of 12
No, they are CISC.

I am familiar more with Intel design and they do decode commands in micro-operations (μops). These μops are more RISC-like.

These two images (from http://www.realworldtech.com/risc-vs-cisc/) should help demonstrate the obvious differences:



Edited by DuckieHo - 1/6/14 at 11:07am
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post #4 of 12
Quote:
Originally Posted by DuckieHo View Post

No, they are CISC.

I am familiar more with Intel design and they do decode commands in micro-operations (μops). These μops are more RISC-like.

As far as I know that makes them more RISC than CISC nowadays as the decoder takes a proportionately smaller surface compared to the execution engine.
 
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post #5 of 12
Quote:
Originally Posted by tpi2007 View Post

As far as I know that makes them more RISC than CISC nowadays as the decoder takes a proportionately smaller surface compared to the execution engine.

They are more RISC-like but the instructions are still very much CISC.


This lecture has a good description... http://www.cs.uni.edu/~fienup/cs240s05/lectures/lec7_2-1-05.htm
Quote:
Outer CISC shell with inner RISC core

Edited by DuckieHo - 1/6/14 at 11:12am
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post #6 of 12
Quote:
Originally Posted by DuckieHo View Post

Quote:
Originally Posted by tpi2007 View Post

As far as I know that makes them more RISC than CISC nowadays as the decoder takes a proportionately smaller surface compared to the execution engine.

They are more RISC-like but the instructions are still very much CISC.

Obviously, x86, as an instruction set, will always be CISC, but the workings inside the CPU are nowadays more RISC than CISC, it's just the front-end that needs to be CISC for compatibility purposes. You get the best of both worlds, the backwards compatibility of x86, and the more efficient RISC architecture executing.
 
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post #7 of 12
Quote:
Originally Posted by tpi2007 View Post

Obviously, x86, as an instruction set, will always be CISC, but the workings inside the CPU are nowadays more RISC than CISC, it's just the front-end that needs to be CISC for compatibility purposes. You get the best of both worlds, the backwards compatibility of x86, and the more efficient RISC architecture executing.

For that backwards compatibility, you do have to pay for the decoder overhead but you are right that it is becoming a smaller cost.


Errrr... there was a very good article I read a number of years ago but how RISC-like is not RISC. In addition to the μops, there was other considerations.....
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post #8 of 12
Thread Starter 
Quote:
Originally Posted by bclk View Post

Not any of the current architectures. There are some historical ones from both Intel and AMD, but nothing current. Look here for more info.

Quote:
Originally Posted by DuckieHo View Post

No, they are CISC.

I am familiar more with Intel design and they do decode commands in micro-operations (μops). These μops are more RISC-like.

These two images (from http://www.realworldtech.com/risc-vs-cisc/) should help demonstrate the obvious differences:

Thanks for the reply.

DuckieHo that link helps a lot! I might have more questions later on, just going to read upon http://www.realworldtech.com/risc-vs-cisc/ also if I have any more question can I message you ? ( I'll also post it down below)
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post #9 of 12
Quote:
Originally Posted by AnnoyinDemon View Post


Thanks for the reply.

DuckieHo that link helps a lot! I might have more questions later on, just going to read upon http://www.realworldtech.com/risc-vs-cisc/ also if I have any more question can I message you ? ( I'll also post it down below)

Found another more low-level detail blog post on the topic: http://scalibq.wordpress.com/2012/02/19/cpus-and-pipelines-how-do-they-work/
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post #10 of 12
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Want are the difference between RISC and CISC... Ive been reading up and know a few things but can anyone explain it to me on here
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