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[WCCF] AMD Pirate Islands : R9 300 Series Roadmap Leak - Page 15

post #141 of 195
" show me a picture of a tree"


"heres a picture of grass"


"thats not a tree"


"theyre both green, so i win"



"...."
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post #142 of 195
Might get this, afterall it has been a while since 7xxx
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post #143 of 195
I can see 96 ROPS with stacked GDDR5 maybe?
post #144 of 195
Quote:
Originally Posted by $ilent View Post

Just admit you are wrong? Is it so hard to do...
Really now you say I'm wrong and thereby state you can't divide 512 by 96? I said it wouldn't end up a whole number but that doesn't mean it can't be done.
Unless you think you can't divide 1/2 or 5/2 because those aren't whole numbers either.
Admitting I'm wrong when I'm right is not in my nature
post #145 of 195
Quote:
Originally Posted by maarten12100 View Post

Really now you say I'm wrong and thereby state you can't divide 512 by 96? I said it wouldn't end up a whole number but that doesn't mean it can't be done.
Unless you think you can't divide 1/2 or 5/2 because those aren't whole numbers either.
Admitting I'm wrong when I'm right is not in my nature

Well... It would be like saying that Broadwell still has quad-core i7s with 11 threads available using hyperthreading, and the i3s have 5.5 threads. Sure, you can divide it, but it ends up 2.75 threads per core. Or maybe Carrizo's flagship will still have two modules but will be a pentacore chip. You can't make the numbers work, and the only way they will is if AMD has totally redone the back-end of these.
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post #146 of 195
Quote:
Originally Posted by CynicalUnicorn View Post

Well... It would be like saying that Broadwell still has quad-core i7s with 11 threads available using hyperthreading, and the i3s have 5.5 threads. Sure, you can divide it, but it ends up 2.75 threads per core. Or maybe Carrizo's flagship will still have two modules but will be a pentacore chip. You can't make the numbers work, and the only way they will is if AMD has totally redone the back-end of these.
I concur on that it didn't have a place in the calculations people were making but saying it can't be divided was not correct and as a wise guy on these forums told me it is better to say something about it than stay silent.
post #147 of 195
Quote:
Originally Posted by maarten12100 View Post

Remainder...
Yeah well as I set it is not a whole number but it is infact an exact number. Just that it isn't a whole number has nothing to do with it being divisible or not. And I do understand what you were getting at but I was just correcting nothing more nothing less.

Trust me on this half my study is math.

I just don't understand why you have to be so persistent. I understand you are from the Netherlands, perhaps you are not familiar with the meaning of this word in English. If x/y != an integer, x is not divisible by y. Yes, you *can* divide them (and get a decimal or irrational number), but they are not considered to be divisible.
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post #148 of 195
Quote:
Originally Posted by Usario View Post

I just don't understand why you have to be so persistent. I understand you are from the Netherlands, perhaps you are not familiar with the meaning of this word in English. If x/y != an integer, x is not divisible by y. Yes, you *can* divide them (and get a decimal or irrational number), but they are not considered to be divisible.
I dunno, back in 4th grade we were dividing all kinds of numbers, not just the ones that did so evenly. I think you can divide any number with any other one.

OT, why do ROPs have to correlate with memory bus width?
post #149 of 195
Quote:
Originally Posted by Dyson Poindexter View Post

I dunno, back in 4th grade we were dividing all kinds of numbers, not just the ones that did so evenly. I think you can divide any number with any other one.

OT, why do ROPs have to correlate with memory bus width?

Please reread my post. Just because you can divide two numbers and get an irrational answer, does not mean these two numbers are divisible. The quotient has to be an integer for the numbers to be considered divisible.

To answer your question, the entire back-end (including memory controllers, ROPs, other stuff) is tied in together in a unit of sorts. If the memory bus width is not divisible by the ROP count that means they can't possibly be in such a unit, since you can't have, say, 5.33... ROPs in a unit. So either the specs are an amateur fake or the entire back end has been re-engineered and the ROPs are decoupled from the memory bus. Every time this has ever happened, it turned out to be the former -- the specs were just BS from someone who knew nothing about GPU architecture. But we'll see.
Edited by Usario - 4/12/14 at 6:01pm
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post #150 of 195
Quote:
Originally Posted by Dyson Poindexter View Post

OT, why do ROPs have to correlate with memory bus width?
Each Pair of RBEs connect to 1 L2 caches which then connect to the IMC.

2 RBEs => 1 L2 cache => 1 Memory Controller (64-bit GDDR5 which is divided into two 32-bit channels)


96 ROPs = 24 RBEs which is 12 L2 Caches => 12 * 64 = 768-bit interface.

96 * 8 = 768
96 * 12 = 1152
96 * 16 = 1536
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