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Are compute units essentially cores?

post #1 of 10
Thread Starter 
e.g. AMD lists its FX 8-series as having 8 cores, but cpu-world.com lists it with 4 compute units and 8 logical processors, and I know logical processors are basically threads. Can't this be considered false advertising? If not, what's the difference between the logical processors of an Intel cpu to an AMD one?
post #2 of 10
AMD Bulldozer architecture uses modules , that's what the "Compute units" are referring to. Each module has 2 integer cores and one floating point unit.

See http://www.bit-tech.net/hardware/cpus/2011/10/12/amd-fx-8150-review/2

* Kaveri (Steamroller is a refresh of Bulldozer) tries to fix some of the scheduling issues and provide floating point via the integrated GCN "GPU" cores




Intel Nehalem/Sandy Bridge/Ivy Bridge/Haswell uses hyperthreading to get more "logical cores" so it has equal performance in integer + floating point. Essentially hyperthreading uses idle time on the core to run a second task. If things need to be done independently of each other, hyperthreading helps. If they need to be done in order, then hyper-threading is not going to help much.

http://www.cpu-world.com/Glossary/H/Hyper-Threading_technology.html
Edited by AlphaC - 4/13/14 at 3:53pm
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post #3 of 10


Indeed, a single piledriver "module" isn't really 2 discrete cores, but rather 2 cores that share resources. 8 "cores" is a stretch, but calling the same chip a quad core isn't really fair either. It just depends on what definition you prefer.

Intel "cores" really are cores, they just have a feature that let's them load/work on 2 threads at once.

Also, this is a hot question for OCN. Prepare for a long argument!
Edited by brucethemoose - 4/13/14 at 3:49pm
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post #4 of 10
Quote:
Originally Posted by bacalaohombre View Post

e.g. AMD lists its FX 8-series as having 8 cores, but cpu-world.com lists it with 4 compute units and 8 logical processors, and I know logical processors are basically threads. Can't this be considered false advertising? If not, what's the difference between the logical processors of an Intel cpu to an AMD one?
By compute modules, AMD means there are 4 "blocks" of computing resources, each one fused together yet capable of processing 2 threads independently. Interger resources (and a couple other things i think) are not shared in a core pair, but the FPU and front ends are shared. In short, it could be considered a core and a half. In this implementation, floating point performance is the limiter as the FPU has to be shared between interger cores, and if the FPU is busy cooking results for one interger core, the other stalls while it waits for the FPU to finish up.

Intel on the otherhand, does logical threads by doubling some front end resources but leaving the rest of the CPU core untouched or with minor tweaks to allow hyperthreading to work. Instead of having extra "hard" resources to handle the extra thread like AMD, Intel instead inserts instructions and data on the secondary logical thread in between gaps in the pipeline of the primary logical thread to make sure the CPU resources are being used to their fullest. This works best in workloads in which the pipeline stalls alot waiting for instructions or data, like video transcoding or distributed computing. However, if the primary logical thread is loaded up with an optimized program that causes few pipeline stalls (say, a short and fast program like hashing or tripcode generation), anything attempting to execute on the second thread will struggle to run as all of the resources are already sucked up processing the primary thread.

I might have gotten some smaller details wrong but that is basically the gist of it.
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post #5 of 10
Thread Starter 
Quote:
Originally Posted by Cyrious View Post

By compute modules, AMD means there are 4 "blocks" of computing resources, each one fused together yet capable of processing 2 threads independently. Interger resources (and a couple other things i think) are not shared in a core pair, but the FPU and front ends are shared. In short, it could be considered a core and a half. In this implementation, floating point performance is the limiter as the FPU has to be shared between interger cores, and if the FPU is busy cooking results for one interger core, the other stalls while it waits for the FPU to finish up.

Intel on the otherhand, does logical threads by doubling some front end resources but leaving the rest of the CPU core untouched or with minor tweaks to allow hyperthreading to work. Instead of having extra "hard" resources to handle the extra thread like AMD, Intel instead inserts instructions and data on the secondary logical thread in between gaps in the pipeline of the primary logical thread to make sure the CPU resources are being used to their fullest. This works best in workloads in which the pipeline stalls alot waiting for instructions or data, like video transcoding or distributed computing. However, if the primary logical thread is loaded up with an optimized program that causes few pipeline stalls (say, a short and fast program like hashing or tripcode generation), anything attempting to execute on the second thread will struggle to run as all of the resources are already sucked up processing the primary thread.

I might have gotten some smaller details wrong but that is basically the gist of it.
aha, thanks very much. so is that the main reason people say that AMD processors aren't fully utilized yet so they don't perform as well as intel ones on many tasks?
post #6 of 10
Quote:
Originally Posted by bacalaohombre View Post

aha, thanks very much. so is that the main reason people say that AMD processors aren't fully utilized yet so they don't perform as well as intel ones on many tasks?
Its one of the reasons as far as i know. The other reason is that AMD is basically going through their "netburst phase". The CPUs are big, power hungry, and are clocked ridiculously high for their single threaded performance (which is about on par with a 3.6ghz nehalem i7. Powerful, yes, but still gets curbstomped by newer chips). When it comes to lightly threaded workloads and general power efficiency, AMD loses big time. The bulldozer architecture is a relatively young one when pitted against ye olde p6, which, unless i am wrong, is what every modern intel chip is based off of. The newer architecture hasnt had time to have all the bugs and bottlenecks ironed out, and thus suffers in performance. The most recent revision though, Steamroller (only available for APUs, since AMD is going into HSA, but thats a whole nother bag of worms there), has definitely brought performance up, and the next revision, Excavator, should finish off ironing out the worst of the problems, and allow AMD to really start with the optimizations. On top of that, HSA is supposed to allow floating point offloading to the on-die GPU, taking the FP deficit the cores are running and turning it into a huge advantage.

Basically, it is an interesting idea on paper, but the execution needs work before it can really shine.

Now, you might be asking yourself: why not simply scale up K10 based chips even further?
The answer to that is that AMD basically hit the limits of the K10 arch in terms of clocking and efficiency. Proof of this is when they crammed what basically amounted to a Phenom II 940 BE (125W) and a Radeon HD 5670 (another 60W) onto a single die inside a 100W power envelope. If AMD had the kind of R&D budget intel has, I'm pretty damn sure they could have pushed K10 harder, but since they already had bulldozer in the pipeline at the time, they decided to shift all of their CPU resources into it, and ultimately their APU line. While bulldozer was effectively a flop, Piledriver, its APU derivatives, and AMDs other APUs have proven to be good budget chips, and are moving enough volume to put AMD back in the black for the first time in years.

TL;DR: they arent as good as intel chips in terms of single threaded performance, but in terms of value, more often than not they curbstomp anything intel can whip up.
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post #7 of 10
Quote:
Originally Posted by Cyrious View Post

The bulldozer architecture is a relatively young one when pitted against ye olde p6, which, unless i am wrong, is what every modern intel chip is based off of.
True, up to a point. All of Intel's current offerings except for the Atom line trace their lineage from the Pentium M Banias core, introduced in 2005. Banias was essentially the old Pentium III Tualatin core, modified by Intel's second design team in Israel to run on the Pentium 4's bus, and with some tweaks to the design that allowed the clock speed to be ramped up. The design was so good that Intel eventually killed off NetBurst, and began developing desktop versions of the new design. It's changed dramatically in the past nine years, though. Modern Intel chips indeed based off the P6, but at this point, it's about like saying that the modern English language is based off the language that Beowulf was written in. In other words: yes, but you have to look really close.

There are rumors that AMD is working along similar lines for its next-generation architecture, combining the best points of the old Phenom II and those of Bulldozer to create something that is better than either of them.
Quote:
Now, you might be asking yourself: why not simply scale up K10 based chips even further?
The answer to that is that AMD basically hit the limits of the K10 arch in terms of clocking and efficiency. Proof of this is when they crammed what basically amounted to a Phenom II 940 BE (125W) and a Radeon HD 5670 (another 60W) onto a single die inside a 100W power envelope. If AMD had the kind of R&D budget intel has, I'm pretty damn sure they could have pushed K10 harder, but since they already had bulldozer in the pipeline at the time, they decided to shift all of their CPU resources into it, and ultimately their APU line.
Correct on all counts. AMD couldn't make the K10 go much faster. Even the die-shrunk version that went into the first APU's wouldn't scale any higher.

The Bulldozer architecture had been under development for some time. In fact, AMD taped out a version of it internally about two years before it was released, but the performance was so anemic that they had to go back to the drawing board. Instead, AMD released a desktop version of their "Istanbul" core Opteron as a competitive response to Intel--we know it as the Phenom II X6 Thuban. The Bulldozer that eventually was released was the re-spin of that. AMD would have been better off if they could have waited and debuted the K11 under the Piledriver design, but they couldn't do anymore with the Phenom II.

It's worth noting that the same thing happened to Intel years before. When AMD brought out the Athlon, the Pentium III couldn't keep pace, and Intel had to rush the Pentium 4 out the door on the awful Willamette design. A 1.4 GHz original P4 couldn't hang with an P3-950. Intel didn't really have a competitive part until they introduced the Northwood core P4 later on. Eventually, their manufacturing prowess let them clock the Northwood high enough to win back to the performance crown--even though AMD's architecture was still vastly more efficient. AMD's problem today is that they don't have access to the world's best fabs (which belong to Intel), and so they can't make FX chips at the speeds necessary to compete with Intel's best.
     
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post #8 of 10
Compute Units are not essentially cores.

One Jaguar CU is four 16h cores.
One Bulldozer CU is two 15h cores.
One Graphic Core Next CU is 64 cores.

A core is not determined by its L1i cache, L1d cache, L2 cache, or by its accelerator.

Each core has its own instruction bus, data bus, control unit, datapath.

The instruction bus feeds the control unit instructions which then get executed in the datapath the end results are then eventually exported out via the data bus.

The dispatch groups instruction bus are not shared between the 15h cores. In Bulldozer, you have instructions going down one path alternating between the two paths every clock. With Steamroller, the instructions can go down both paths per clock.

The control unit is not shared between the 15h cores. Each x86-64 core in the 15h compute unit has its own scheduler which is technically the control unit.

The datapath is not shared between the 15h cores. Each core has its own ALUs and AGUs.

The data bus is not shared between the 15h cores. Each core has its own in and out for data.

15h cores are not two threads sharing a core{single instruction bus, data bus, control unit, and datapath}. Instead, it is two separate cores each with their own instruction bus, data bus, control unit, and datapath.

Intel's Hyperthreading Core is two threads sharing a core. The two threads compete for; {instruction bus usage, data bus usage, control unit usage, datapath usage.} as there is only one of each of those in the core.

AMD's Bulldozer Compute Unit/Module is two threads each using their own core. The two threads do not compete for; {instruction bus usage, data bus usage, control unit usage, datapath usage.} as there are two of each in the compute unit or module.
Edited by Seronx - 4/14/14 at 1:23am
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post #9 of 10
Is 8 cylinders at 5000rpm more powerful than 4 cylinders at 3000rpm? There is no answer because we don't know enough about the engines. An 8 cylinder engine is an 8 cylinder engine whether it's 200HP or 600HP.

No false advertising required. Misleading perhaps, as "core count" is being sold as a feature, even though it is as meaningless as cylinder count in an engines. Just like ghz is as meaningless as RPM.
     
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post #10 of 10
Quote:
Originally Posted by mdocod View Post

Is 8 cylinders at 5000rpm more powerful than 4 cylinders at 3000rpm? There is no answer because we don't know enough about the engines. An 8 cylinder engine is an 8 cylinder engine whether it's 200HP or 600HP.

No false advertising required. Misleading perhaps, as "core count" is being sold as a feature, even though it is as meaningless as cylinder count in an engines. Just like ghz is as meaningless as RPM.
Car analogies are pretty far fetched.

Street: Workload
Car Construction: Architecture
Car Build: Bulk or SOI
Car Engine: MIPS, FUSI, RMG + Fabrication Node
Car: A Core
Amount of Drivers: Threads

The Intel "Bridge/Well" Supercar;
- Core 2 based construction. = The design of the car.
- RMG + 32nm/22nm/14nm bulk. = Fast engine / Bulk Steel body for Bulk and Bulk FinFETs.
- Amount of drivers per car = 2. = Two drivers are competing for the car.

The AMD "Dozer" Supercar;
- Dozer based construction = The design of the car.
- MIPS + 32nm SOI/28nm Bulk = Slow engine / Carbon Fiber body for SOI parts and Slow engine / Bulk Steel for bulk parts.
- Amount of drivers per car = 1. = No drivers are competing for the car.

On a street the Haswell-DT Supercars; there can be four cars with two drivers each.
On a street the Dozer-FX Supercars; there can be eight cars with one driver each.


Highway = Heavy workoad / Rural Street = Little to no workload
Car construction; can vary.
Car build: Bulk = Bulk Steel can be refined to be less heavy but is still bulk steel / SOI = Carbon Fiber very light material can allow a slow engine car to be as fast as a fast engine car.
Car Engine = MIPS(Gate First) = Slow Engine(Low Top Speed) / FUSI(Gate Last) = Medium Engine (Average Top Speed) / RMG(Gate Last) = Fast Engine (Fastest Top Speed)
Amount of cars = Amount of cores
Amount of drivers per car = Amount of threads that can be on a core.

Car construction determines how fast or slow the car can actually go. While the build and engine can determine the top speed and lowest speed.
Edited by Seronx - 4/14/14 at 12:28pm
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