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[WCCF] AMD’s New High Performance Processor Cores Coming Sometime in 2015 – Giving Up on Modular Architecture - Page 3

post #21 of 485
Quote:
Originally Posted by PureBlackFire View Post

I agree. although, excavator will be CMT.

Indeed. I have no idea how can they properly juggle between CMT and SMT. By far the most intriguing chip of the last 3 years at least.
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post #22 of 485
I do hope this is true.

Hail Jimm Keller!
post #23 of 485
CMT is here to stay, it does not compete with SMT. The next CMT architecture is CCMT which is Concurrent Cluster Multithreading, which is CMT and SMT combined.

In the case of a 15h like architecture it would be like;

ALU/AGLU cluster 0 + ALU/AGLU cluster 1 + ALU/AGLU cluster 2 + ALU/AGLU cluster 3. All these clusters are a single thread and share a unified scheduler and retire, etc.

Each cluster has their own registers and a L0d cache that is write through to L1d. Which in turn that is also write through to the L2 cache.
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post #24 of 485
Quote:
Originally Posted by geoxile View Post

I thought the performance problem with CMT was that both cores (of a module) weren't fed quickly enough.

While this might be a peripheral problem, one would expect that Steamroller would have fixed most of BD's issues if this was the main problem. Feeding them faster seemed to help, especially with the gains SR saw in multithreaded applications, but it didn't help all that much.
Edited by PiOfPie - 5/4/14 at 2:12pm
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post #25 of 485
Quote:
Originally Posted by Seronx View Post

CMT is here to stay, it does not compete with SMT. The next CMT architecture is CCMT which is Concurrent Cluster Multithreading, which is CMT and SMT combined.

In the case of a 15h like architecture it would be like;

ALU/AGLU cluster 0 + ALU/AGLU cluster 1 + ALU/AGLU cluster 2 + ALU/AGLU cluster 3. All these clusters are a single thread and share a unified scheduler and retire, etc.

Each cluster has their own registers and a L0d cache that is write through to L1d. Which in turn that is also write through to the L2 cache.

This makes more sense. I doubt AMD would double back.
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post #26 of 485
Quote:
Originally Posted by Seronx View Post

CMT is here to stay, it does not compete with SMT. The next CMT architecture is CCMT which is Concurrent Cluster Multithreading, which is CMT and SMT combined.

In the case of a 15h like architecture it would be like;

ALU/AGLU cluster 0 + ALU/AGLU cluster 1 + ALU/AGLU cluster 2 + ALU/AGLU cluster 3. All these clusters are a single thread and share a unified scheduler and retire, etc.

Each cluster has their own registers and a L0d cache that is write through to L1d. Which in turn that is also write through to the L2 cache.

Four integer clusters in a module? What are they going to do, double up the scheduler again? And then leave it with a 4:1 integer:FP core ratio, or double up on the FPU as well (and would that mean having two separate FPUs or a 512-bit FPU with four FMACs that builds upon the current Flex FP to do two 256-bit ops, four 128-bit ops, etc, concurrently... or something else)? I'm no expert but ditching CMT altogether sounds better to me.
Edited by Usario - 5/4/14 at 2:22pm
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post #27 of 485
I think the whole SMT, CMT, and VMT situation has been confused.

Bulldozer/Piledriver/Steamroller have parts that are VMT.

Bulldozer/Piledriver; Fetch/Decode is VMT and so is the front end for the FPU.
Steamroller; Fetch is VMT and so is the front end for the FPU.
Excavator; Everything is SMT, there is a fetch for each core, there is a decode for each core. While the front-end for the FPU can receive instructions from both cores at the same time.

Excavator gives up the VMT structure that is in Steamroller, Piledriver, and Bulldozer for SMT.
Quote:
Originally Posted by Usario View Post

Four integer clusters in a module? What are they going to do, double up the scheduler again? And then leave it with a 4:1 integer:FP core ratio, or double up on the FPU as well (and would that mean having two separate FPUs or a 512-bit FPU that builds upon the current Flex FP to do two 256-bit ops, four 128-bit ops, etc, concurrently)? I'm no expert but ditching CMT altogether sounds better to me.
The current implementation is;
One core has one execution/memory cluster.

The future of CMT is CCMT which is;
One core with two to eight execution/memory clusters.

The FPU in Bulldozer/Piledriver/Steamroller/Excavator is not part of the core but part of the module. AMD will keep the FPU consistent with the capabilities of the x amount of clusters.

So, if you have a CCMT module with 8 cores and each core has 8 clusters; then you'll have 64 x-bit FPUs.
Edited by Seronx - 5/4/14 at 2:29pm
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post #28 of 485
Please be true, I need my Phenom III
post #29 of 485
This sounds like a good decision to return to essence.
I suppose this would revert the quoted L1d L1i load-store cache bottleneck. I lack the knowledge whether the previous architecture could issue sufficient commands for both cores(4 integer threads) + the fpu at the same time to begin with, but I have come across opinions that the front end was more than capable in contrast to the cache structure. I wonder how the microarchitecture would change after this.
Edited by mtcn77 - 5/4/14 at 2:45pm
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post #30 of 485
Does this mean a new chipset?
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