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[WCCF] AMD’s New High Performance Processor Cores Coming Sometime in 2015 – Giving Up on Modular Architecture - Page 42

post #411 of 485
Quote:
Originally Posted by Kuivamaa View Post

Vishera vs Zambezi, both clocked@4Ghz. I post this because they are concerned of the bench nature which may explain the difference in results among reviews.

There does appear to be an advantage in Piledrivers favor with regard to cache performance, but these are not consistently represented in benchmarks, nor are they explained by the changes shown in the chart you mention. The only difference listed between a BD and PD in that chart is a one cycle (5%) greater L2 latency for BD.

I strongly suspect the differences in measured real world performance, and in cache benchmarks, have more to do with the other changes PD implemented, than with changes to the caches themselves. If there were a significant change to the cache, in and of itself, it would present itself more consistently across varying cache centric benchmarks.

Not saying or implying their aren't differences in cache between the two, but I think the effects of these differences are being overemphasized, with other differences possibly being misattributed to them.
Quote:
Originally Posted by Seronx View Post

They share the same coherency level, they are both last level caches.

How are they both last level cache? I have never heard this anywhere. Do you have a source?

I know AMD's cache's are exclusive, but that doesn't make them all last level. Neither does being able to skip cache levels. Neither does chips of the same architecture that lack the L3 cache level.
Quote:
Originally Posted by Seronx View Post

They share the same coherency level, they are both last level caches.
The bench image, I posted is single-threaded AIDA64. So, it is the lowest latency needed with the least amount of coherency.

Sandra is completely multithreaded and is showing the speeds of coherency.

They both show fairly clear distinctions between the L2 and L3 cache levels.
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post #412 of 485
Quote:
Originally Posted by Blameless View Post

How are they both last level cache?
The L3 cache is simply an extension to the L2. If the L2 can't hold any more put the oldest lines into the L3. Anything in the L3 has to be placed into the L2 to get out.
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post #413 of 485
CMT and AMD CPus are OKAY! They are GOOD! >Little more optimization and lower lvl API and they will be very strong.

Only thing that i hate on amd is "WHY they use old chipset"? WHY? WHY no good ITX,mATX AM3+? So many little thing that makes people rethink their decision. I am very pleased with FX 6300 but these chipsets are really OLD!


What i wanted to see from steamroller +15% in MT perfromance and 15% less power consumption. New chipsets, better memory controller lower lantency in L3 cache.
Edited by Themisseble - 5/15/14 at 4:49am
post #414 of 485
I don't understand the demand for L3 cache, it's basically irrelevant under this current architecture. Adding it won't improve performance. However if they did add a new type of cache that acted as a buffer threaded through the GPU cores it'd be 10 times faster than L3 cache as FPGA is much more responsive in a memory environment. L3 on cpus today is silly, a waste of space.
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post #415 of 485
Quote:
Originally Posted by Seronx View Post

The L3 cache is simply an extension to the L2. If the L2 can't hold any more put the oldest lines into the L3. Anything in the L3 has to be placed into the L2 to get out.

Even if the L3 is essentially a victim cache, that doesn't mean the L2 is the last-level cache.

I suppose this is more a semantic argument than anything.
Quote:
Originally Posted by Themisseble View Post

New chipsets, better memory controller lower lantency in L3 cache.

The larger issue with AMD's BD/PD/SR caches seems to be that the L1 is write through, rather than write back. This means that writes to the L1 have to be made to the L2 at the same time, so L1 writes are held up by the slow L2.
Quote:
Originally Posted by SpeedyVT View Post

L3 on cpus today is silly, a waste of space.

Maybe on some, but not on all.

AMDs APUs and some of the Athlons do well without the L3, but I highly doubt any of Intel's modern mainstream or high-end parts could be remotely viable without their L3.
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post #416 of 485
Quote:
Originally Posted by SpeedyVT View Post

I don't understand the demand for L3 cache, it's basically irrelevant under this current architecture. Adding it won't improve performance. However if they did add a new type of cache that acted as a buffer threaded through the GPU cores it'd be 10 times faster than L3 cache as FPGA is much more responsive in a memory environment. L3 on cpus today is silly, a waste of space.
Athlon II vs Phenom II shows that L3 gives a nice boost. Especially when you oc the NB on Phenom II. Overclocking NB on Athlon II won't bring a huge improvement while doing the same on Phenom II gives a nice improvement.
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post #417 of 485
Quote:
Originally Posted by Pawelr98 View Post

Athlon II vs Phenom II shows that L3 gives a nice boost. Especially when you oc the NB on Phenom II. Overclocking NB on Athlon II won't bring a huge improvement while doing the same on Phenom II gives a nice improvement.

While L3 might have given Stars a boost, that doesn't seem to be the case for the Construction Cores. Perhaps it would if the L1 was better designed as Blame said, but in its current implementation, it's wasting a ton of die space for very little effect on Zambezi/Vishera/et al.
Edited by PiOfPie - 5/15/14 at 10:25am
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post #418 of 485
Quote:
Originally Posted by Seronx View Post

The L3 is that high because it is fused with the L2 cache.

AMD's structure of cache;
L1 + L2/L3 + System Memory

The L2 and L3 in AMD are basically the same level of cache.



Intel's structure of cache;
L1 + L2 + L3 + System Memory

The L2 and L3 in Intel are separate levels.

How are different caches with different positions (module level vs chip level) and different associativity and different latencies fused in any way? Even your own data indicates far different caches due to latency differences.
post #419 of 485
Quote:
Originally Posted by hajile View Post

How are different caches with different positions (module level vs chip level) and different associativity and different latencies fused in any way? Even your own data indicates far different caches due to latency differences.
The L3 ctrl has to communicate with the L2 ctrl to get anything done. You can tell that the L3 is mostly meant for reads not writes simply by the GB/s.
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post #420 of 485
Quote:
Originally Posted by Seronx View Post

The L3 ctrl has to communicate with the L2 ctrl to get anything done. You can tell that the L3 is mostly meant for reads not writes simply by the GB/s.
The L2 must communicate with the L1 to get anything done. The L1 must interact with the PC and registers to get anything done. This means nothing as far as the relationship between them.

I recommend you educate yourself about how cache works before making such statements. Here's a decent place to begin
http://alasir.com/articles/cache_principles/
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