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[WCCF] AMD’s New High Performance Processor Cores Coming Sometime in 2015 – Giving Up on Modular Architecture - Page 43

post #421 of 485
Quote:
Originally Posted by hajile View Post

The L2 must communicate with the L1 to get anything done. The L1 must interact with the PC and registers to get anything done. This means nothing as far as the relationship between them.

I recommend you educate yourself about how cache works before making such statements. Here's a decent place to begin
http://alasir.com/articles/cache_principles/
All of that is irrelevant to the method of how L2 and L3 interact with each other in AMD architectures.

The L3 does not communicate with DRAM or to any parts of the system. DRAM stores reads directly to the L2 or sends it directly through the Hypertransport connection. The L3 does not exist except to the L2 cache and its main job is to handle L2 evictions not L3 evictions which are the L2's job. In fact, it is better to refer the L3 cache as the L2.5 cache. As it extends the L2's cache capacity preventing any extra misses.
Edited by Seronx - 5/15/14 at 2:51pm
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post #422 of 485
Quote:
Originally Posted by PiOfPie View Post

While L3 might have given Stars a boost, that doesn't seem to be the case for the Construction Cores. Perhaps it would if the L1 was better designed as Blame said, but in its current implementation, it's wasting a ton of die space for very little effect on Zambezi/Vishera/et al.
Zambezi/Vishera also have overclockable NB. But so far no benches on that.
Maybe the low NB clock is holding back the cache/IMC just like in a Phenom II.
Edited by Pawelr98 - 5/15/14 at 3:21pm
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post #423 of 485
I've done pretty extensive testing of NB overclocking on PD. Performance gains are slim to non-existent. Depends on workload. Goes best with system memory performance tuning.
     
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post #424 of 485
Quote:
Originally Posted by mdocod View Post

I've done pretty extensive testing of NB overclocking on PD. Performance gains are slim to non-existent. Depends on workload. Goes best with system memory performance tuning.
What kind of clocks can the PD NB achieve ? BD/PD have better memory controller(up to 1866mhz) so maybe the performance gain shows with 2000+mhz memory. On Phenom II even on 1333/1600mhz memory the gain is clearly visible.2000mhz to 3000mhz is like night and a day.In my case it was really visible in SRIV where I observed a huge jump in min FPS.
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post #425 of 485
that's the advantage of CMT. It was a architecture that design for multitask
post #426 of 485
Quote:
Originally Posted by Seronx View Post

You can tell that the L3 is mostly meant for reads not writes simply by the GB/s.

This problem goes all the way up to and including the L1, which is write-through on BD and PD. Read performance is fine, write performance is abysmal because you cannot write to the L1 independently of the L2.
Quote:
Originally Posted by Seronx View Post

The L3 does not communicate with DRAM or to any parts of the system. DRAM stores reads directly to the L2 or sends it directly through the Hypertransport connection.

Why would memory traffic on a single socket setup ever touch Hypertransport?
Quote:
Originally Posted by Seronx View Post

The L3 does not exist except to the L2 cache and its main job is to handle L2 evictions not L3 evictions which are the L2's job. In fact, it is better to refer the L3 cache as the L2.5 cache. As it extends the L2's cache capacity preventing any extra misses.

Yes, it's essentially a giant victim cache. I still think most would consider it it's own cache level regardless.
Quote:
Originally Posted by Pawelr98 View Post

What kind of clocks can the PD NB achieve ?

Not high, at least for 24/7 setups that aren't on extreme cooling.
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post #427 of 485
Quote:
Originally Posted by Blameless View Post

Why would memory traffic on a single socket setup ever touch Hypertransport?
To get to hard drives, graphic processors, and the internet.

AMD architectures with L3 communicate to the outside with an external Northbridge via Hypertransort.
Quote:
Originally Posted by Blameless View Post

This problem goes all the way up to and including the L1, which is write-through on BD and PD. Read performance is fine, write performance is abysmal because you cannot write to the L1 independently of the L2.
Actually, the write through is only part of the L1D and its decoupled from the L2 with the 4KB WCC.

L1D WT to WCC
WCC WB to L2
L2 WB to L3
L2 WB to RAM
Edited by Seronx - 5/15/14 at 7:02pm
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post #428 of 485
Quote:
Originally Posted by Seronx View Post

All of that is irrelevant to the method of how L2 and L3 interact with each other in AMD architectures.

The L3 does not communicate with DRAM or to any parts of the system. DRAM stores reads directly to the L2 or sends it directly through the Hypertransport connection. The L3 does not exist except to the L2 cache and its main job is to handle L2 evictions not L3 evictions which are the L2's job. In fact, it is better to refer the L3 cache as the L2.5 cache. As it extends the L2's cache capacity preventing any extra misses.

What evidence do you have that main memory reads directly into L2 instead of the NB?

The point of ANY higher cache is to extend the size of lower caches in order to increase cache hit rate. What I stated (irrelevance of cache interaction) is always relevant. L2 also does not communicate with any part of the system outside of the specific module. When data is needed, the northbridge checks if the data is in the L3. If not, it sends a system request to main memory. The only change from the ordinary (for x86) is that L2⊄L3 (for that matter, L1⊄L2 since a subset is not guaranteed for at all times -- making the L1/L2 relationship identical to the L2/L3 in the manner you speak of). The purpose of this has little to do with CMT and much more to do with keeping individual CMT modules more isolated, enhancing multi-chip interconnect hit rates, and making communication with integrated GCN modules easier

Your statement (that L3 must communicate with L2) is meaningless as the point of any cache is to communicate with lower levels. The view of L3 as an extension of L2 is the same as saying that L2 is an extension of L1 (and equally as pointless).

Your other statement (that you can tell that the L3 is mostly meant for reads not writes simply by the GB/s.) is false and shows a misunderstanding of cache design. ALL cache in typical processors reads far faster than it writes (your own chart shows this) both because reads require no lock and because changing NAND gates takes more time than checking the current state of a gate. Finally, L3 is higher latency because it uses a more space-efficient design (Uses fewer transistors for a given unit of memory). The higher bandwidth is a function of a wider bus. Your statement about L3 is non-sequitur.

As to my opinion, AMD should have switched to on-chip eDRAM for L3 like IBM did years ago. It offers a much better memory/area rate than typical L3 without a huge change in latency (instead trading off cache persistance -- that is, it needs to be refreshed frequently to prevent memory decay).








Edited by hajile - 5/15/14 at 7:50pm
post #429 of 485
Quote:
Originally Posted by hajile View Post

What evidence do you have that main memory reads directly into L2 instead of the NB?
The DRAM prefetches/fetches through a queuing interface. This queuing interface goes to the "core" prefetcher which is installed into the module-L2.

The "northbridge" on die with the MCT creates the logs of system memory. This memory is then stored in the logs in the external northbridge aka the I/O MMU.
Quote:
Originally Posted by hajile View Post

The point of ANY higher cache is to extend the size of lower caches in order to increase cache hit rate. What I stated (irrelevance of cache interaction) is always relevant. L2 also does not communicate with any part of the system outside of the specific module. When data is needed, the northbridge checks if the data is in the L3. If not, it sends a system request to main memory. The only change from the ordinary (for x86) is that L2⊄L3 (for that matter, L1⊄L2 since a subset is not guaranteed for at all times -- making the L1/L2 relationship identical to the L2/L3 in the manner you speak of). The purpose of this has little to do with CMT and much more to do with keeping individual CMT modules more isolated, enhancing multi-chip interconnect hit rates, and making communication with integrated GCN modules easier
This is not true in the sense of AMD vs Intel.

The L2 in Intel's architecture is a coalescing buffer between the L1 and the larger L3.

The L2 in AMD's architecture is the final level of cache before system ram, the L3 is a victim to the L2 which slightly extends the L2 storing parameters.

Everything in Bulldozer's L3 must have been originating from the L2 cache. While Intel's L3 isn't required to hold anything from lower or higher levels of RAM.
Edited by Seronx - 5/15/14 at 9:13pm
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post #430 of 485
Quote:
Originally Posted by Blameless View Post

Not high, at least for 24/7 setups that aren't on extreme cooling.
So like ~2600mhz or less on water/air ?

2800-3000mhz is common for PhenomII E0(thuban)/C3(X2,X3,X4). I run 3ghz 24/7 at 1275mV on my Thuban. My previous 965(the one that sits in my server right now) was running 2600mhz at 1.1V (stock volts) and could run 2800-3000mhz at 1.2V back when I used it in my main rig.
Phenom II cores were held back by slow NB(50% OC gives a huge boost). I just want to see the PD behaviour on increased(not 200-400mhz more but like 600-800mhz more if that's even possible with PD) NB clocks.
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