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post #9851 of 10651
the hell did I just saw? lachen.gif

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post #9852 of 10651
Hope you all don't mind that I'm really going to enjoy this:

4.2 Ghz overclock
5 consecutive runs of Realbench Benchmark.
Idle cache voltage: 0.594-0.660v




So. Way better than adaptive cache could ever achieve.

Let's recap, shall we?

1) Ignorant noob asks a bunch of questions. Initially gets polite responses that quickly degrade into contemptuous abuse by the Big Brains.

2) Ignorant noob comes up with two mostly functional ways of getting around Intel's problem. First by himself, second from assist by Raja's response to scone. Sadly, both workarounds were limited, but more than anyone else seemed to have come up with.

3) Aside from jpmboy, no credit given, at all, by anyone, to the ignorant noob for accomplishing those.

4) Ignorant noob is the only one who notices or cares that, despite the offset issue in tistou's video, *man*, those idle voltages are *really low*. Ignorant noob insisting that there's something there earns a whole lot more derision from the Big Brains.

5) Ignorant noob, with NO ASSIST FROM ANY OF THE BIG BRAINS, figures out what's doing it.

6) Ignorant noob figures out the precise C-States setting necessary to duplicate the effect.

7) Ignorant noob tests this successfully, which results in a solution to the problem that is *better* than what we were trying to accomplish.

8) Sadly for Praz, he won't be able to offer this solution to anyone, because he's not reading this. I guess the rest of you will have to fill in for him.

9) Ignorant noob will almost certainly still not get any credit for this from the Big Brains, even though (aside from Praz, of course), they'll probably use the answer that Ignorant Noob came up with from now on

10) Other posters here, who see this, will (in reality) have the ignorant noob to thank for getting their idle voltages lower than they could have ever hoped for with Adaptive Cache. Not any of the Big Brains..

11) But I am content that every time the Big Brains give this solution to another poster who asks about this problem, and that poster thanks *them*, they'll die just a little bit inside.


Cause, as we all know, it's not providing multiple solutions to a problem that matter, it's how many big technical words you can get into a post.

To Praz, and to a lesser extent scone, for your insufferable condescension and rudeness, and whose "answers" actually pointed at all times AWAY from the final solution: allow me to say: GFY.
    
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post #9853 of 10651
Quote:
Originally Posted by mus1mus View Post

the hell did I just saw? lachen.gif

Hello

The best thing to come out of this discussion has been the pictures.

Edit: Fixed.
Edited by Praz - 7/31/16 at 4:56pm
post #9854 of 10651
Quote:
Originally Posted by Qwinn View Post

Hope you all don't mind that I'm really going to enjoy this:
Warning: Spoiler! (Click to show)
4.2 Ghz overclock
5 consecutive runs of Realbench Benchmark.
Idle cache voltage: 0.594-0.660v




So. Way better than adaptive cache could ever achieve.

Let's recap, shall we?

1) Ignorant noob asks a bunch of questions. Initially gets polite responses that quickly degrade into contemptuous abuse by the Big Brains.

2) Ignorant noob comes up with two mostly functional ways of getting around Intel's problem. First by himself, second from assist by Raja's response to scone. Sadly, both workarounds were limited, but more than anyone else seemed to have come up with.

3) Aside from jpmboy, no credit given, at all, by anyone, to the ignorant noob for accomplishing those.

4) Ignorant noob is the only one who notices or cares that, despite the offset issue in tistou's video, *man*, those idle voltages are *really low*. Ignorant noob insisting that there's something there earns a whole lot more derision from the Big Brains.

5) Ignorant noob, with NO ASSIST FROM ANY OF THE BIG BRAINS, figures out what's doing it.

6) Ignorant noob figures out the precise C-States setting necessary to duplicate the effect.

7) Ignorant noob tests this successfully, which results in a solution to the problem that is *better* than what we were trying to accomplish.

8) Sadly for Praz, he won't be able to offer this solution to anyone, because he's not reading this. I guess the rest of you will have to fill in for him.

9) Ignorant noob will almost certainly still not get any credit for this from the Big Brains, even though (aside from Praz, of course), they'll probably use the answer that Ignorant Noob came up with from now on

10) Other posters here, who see this, will (in reality) have the ignorant noob to thank for getting their idle voltages lower than they could have ever hoped for with Adaptive Cache. Not any of the Big Brains..

11) But I am content that every time the Big Brains give this solution to another poster who asks about this problem, and that poster thanks *them*, they'll die just a little bit inside.


Cause, as we all know, it's not providing multiple solutions to a problem that matter, it's how many big technical words you can get into a post.

To Praz, and to a lesser extent scone, for your insufferable condescension and rudeness, and whose "answers" actually pointed at all times AWAY from the final solution: allow me to say: GFY
.

post the corresponding bios screenshot!
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post #9855 of 10651
Quote:
Originally Posted by Praz View Post

Hello

The best thing to come out of this discussion has been the pictures.

Oh. Oh Dear God. I never could have even *asked* for a more hilarious response to my last post than that.

That just made my week.
    
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post #9856 of 10651
Quote:
Originally Posted by Qwinn View Post

Oh. Oh Dear God. I never could have even *asked* for a more hilarious response to my last post than that.

That just made my week.

As you can see below I did not quote you. Thank the forum for the minute of glory you thought I gave you.


post #9857 of 10651
Quote:
Originally Posted by Jpmboy View Post

post the corresponding bios screenshot!

No changes to cache settings, I'm still running Offset Mode +0.27v like I always have.

These are the settings doing all the work.



Quote:
Originally Posted by Praz View Post

As you can see below I did not quote you. Thank the forum for the minute of glory you thought I gave you.

ROFLMAO... please, make it stop! Someone, please, explain what just happened to him. I'm starting to feel sorry for him, which I didn't think was possible.
    
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post #9858 of 10651
Quote:
Originally Posted by Praz View Post

As you can see below I did not quote you. Thank the forum for the minute of glory you thought I gave you.

Warning: Spoiler! (Click to show)

Very true.

With the kind of bashing the past couple of days in these thread, arrgh.

FWIW, if that worked for you, fine. If you feel like breaking through a boarder, fine. No need for some unneeded insults here and there.
post #9859 of 10651
Quote:
Originally Posted by Qwinn View Post

No changes to cache settings, I'm still running Offset Mode +0.27v like I always have.

These are the settings doing all the work.


ROFLMAO... please, make it stop! Someone, please, explain what just happened to him. I'm starting to feel sorry for him, which I didn't think was possible.

ya, erm - If you had just said you were looking for a way to drop voltage at idle, and not being quixotic about Adaptive Voltage, anyone here would have suggested C-States.

ps> c'mon man, you had to laugh at that monkey. if not...


Edited by Jpmboy - 7/31/16 at 5:16pm
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post #9860 of 10651
Quote:
Originally Posted by Jpmboy View Post

ya, erm - If you had just said you were looking for a way to drop voltage at idle, and not being quixotic about Adaptive Voltage, anyone here would have suggested C-States.

Um seriously?

I think I mentioned it like 12 times.

How about here?
Quote:
Originally Posted by Qwinn View Post

Those of us trying to get this working have already acknowledged this, and are trying non-intuitive settings as a workaround to achieve the desired RESULT of a good cache overclock with lower idle voltage than offset mode can provide. That's the point of Adaptive Cache, right?

tistou and I both discovered workarounds that achieve the intended result of low idle voltage. Mine had the flaw that it involved a crazy high voltage setting in the BIOS. tistou's was better than mine - he didn't have to put in any crazy settings, and he *still* got results. In that video, he's showing 0.716v cache voltage at idle. That's lower than me using 0 offset!

He's also told us that what he's getting is a significant drop from the best idle voltage he can get with offset mode. I think he said he's getting a full 0.2v lower idle voltage. That's pretty significant. It'd be more than good enough for me.
    
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