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post #111 of 114
Quote:
Originally Posted by Themisseble View Post

These benchmarks shows opposite

Indeed !
AMD transfers 256 bits in two cycles instead of one. Even with that much slower AVX throughput, L1, L2, L3 and memory bandwidth are lot slower for this type of abnormal AVX operation.
I am sure Excavator will be a garbage APU as well in terms of AVX performance, let alone AVX2 and so will be Zen in 2016 with AVX3.2.
Adding decoder and more pipelines will not solve anything. 3rd quality garbage cache configuration with garbage memory controller are not for AVX, let alone AVX2 and AVX3.2. Intel is light year ahead in these terms.

AMD should just focus on APU. Integrated GPU cores with CPU's cache coherency is what interests me and might change the game.
But APUs will always be mediocre no matter how many GPU cores they add if AMD still can't make a proper compiler for it.
Edited by sumitlian - 10/20/14 at 3:52pm
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post #112 of 114
Quote:
Originally Posted by sumitlian View Post

Indeed !
AMD transfers 256 bits in two cycles instead of one. Even with that much slower AVX throughput, L1, L2, L3 and memory bandwidth are lot slower for this type of abnormal AVX operation.
I am sure Excavator will be a garbage APU as well in terms of AVX performance, let alone AVX2 and so will be Zen in 2016 with AVX3.2.
Adding decoder and more pipelines will not solve anything. 3rd quality garbage cache configuration with garbage memory controller are not for AVX, let alone AVX2 and AVX3.2. Intel is light year ahead in these terms.

AMD should just focus on APU. Integrated GPU cores with CPU's cache coherency is what interests me and might change the game.
But APUs will always be mediocre no matter how many GPU cores they add if AMD still can't make a proper compiler for it.

Would be big difference if AMD would make bulldozer with one fast 256bit FPU ... So 2 cores in module could share it (maybe this is not possible- i am not expert).... maybe was just amd falling behind...

Better FPu better CPu for gaming. Yes FX also phenoms have great integer performance... but lacking on FPU. AMD didnt improve their FPU for a long time. Maybe 5-15%....

So basically FX 8350 is true 8 core.... but who need 8 core with 8 slow FPU units?
post #113 of 114
I'm pretty sure it IS one FPU that's strictly shared, each core only getting 50% usage i.e. like a 128-bit unit
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post #114 of 114
Quote:
Originally Posted by geoxile View Post

I'm pretty sure it IS one FPU that's strictly shared, each core only getting 50% usage i.e. like a 128-bit unit
It is dynamically load balanced, thus we can't say it is a 50/50 share.

The FPU in Bulldozer <-> Steamroller, does not process 256-bit ops but two 128-bit ops for AVX. When the divided AVX operation is executed, it can be done out of order.

Executing both upper and lower sides of the operation on the upper and lower datapath of the FPU takes 1 cycle.
Executing both upper and lower sides of the operation on the upper or lower datapath of the FPU takes 6 cycles.

Operations not related or dependent on that AVX op can be executed in the next cycle.

FP128 to FP256 has another effect.
AVX256 = Two macro-ops with FP128
AVX256 = One macro-op with FP256

So, with Excavator, it could decode 4/four AVX256 operations. Rather, than just 2/two AVX256 operations, if that given decode cycle was FPU only.

Decode has to be changed to support one macro-op AVX.
Retire has to be changed to support one macro-op AVX.
The FPU has to be completely overhauled to support one macro-op AVX.
The LD/ST also has to be overhauled to support 256-bit LD/ST operations that come with one-macro AVX.

FP128 op = 1 x 128-bit "Computational" op + 1 x 128-bit "Memory" op <= AVX in FP128 takes two of these.
FP256 op = 1 x 256-bit "Computational" op + 1 x 256-bit "Memory" op <= AVX in FP256 takes one of these.

With that "Excavator" is a new microarchitecture, if it supports FP256. "Excavator" has the potential to fix everything in regards to PR with Cluster-based Multithreading.
Edited by Seronx - 10/20/14 at 6:24pm
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