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[RWT] What’s Next for Moore’s Law? For Intel, III+V = 10nm QWFETs - Page 2

post #11 of 12
Graphene, boron nitride, molybdenum disulphide, phosphorene, silicene, germanene etc etc.....once we've figured out production methods to harness these materials.
post #12 of 12
The author says silicon is what is making wafer costs higher as process size goes down, but I thought that silicon didnt actually contribute much if at all to the rising wafer costs? The contributing facter is the ability to etch features at smaller sizes, regardless of what you are etching in. This rising costs is because current tech required a move to double patterning which is two passes to etch features. This means higher failure rate if something is not done right in either pass and higher costs from the time and energy requirements of multiple passes. Costs will increase against sub 10nm as we move from double to triple or quad patterning to get even smaller. The driving force of lowering costs is not a move from silicon to something else, it is a move to a different lithography technology. All fab's (Intel, Samsung, Global Foundries, TSMC) are waiting on extreme ultraviolet lithography. Until then costs will keep going up as we get smaller.

That is it for costs, but actually using a material for sub 10nm is also another matter. That is the issue I think the author is trying to discuss but getting the info wrong. Silicon can only go so far because of it's molecular structure and what we can do with it. We need a new substance that has a smaller structure and better properties to combat quantum effects within the CPU as we get too small.
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7700K AS Rock Z170 OC Formula Titan X Pascal 2050MHz 64GB DDR4-3200 14-14-14-34-1T 
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Win 10 Pro x64 AMH A399U E-Element mechanical, black switches, Vortex b... EVGA G3 1kw 
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Lian-Li PC-V1000L Redragon M901 LH Labs Pulse X Infinity DAC Custom built balanced tube amp with SS diamond ... 
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Overclock.net › Forums › Industry News › Hardware News › [RWT] What’s Next for Moore’s Law? For Intel, III+V = 10nm QWFETs