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[Various] AMD HBM presentation and slides

post #1 of 208
Thread Starter 
Quote:
Originally Posted by Anandtech 
Bringing this deep dive to a close, as the first GPU manufacturer to be shipping an HBM solution – in fact AMD expects to be the only vendor to ship an HBM1 solution – AMD has set into motion some very aggressive product goals thanks to the gains from HBM. Until we know more about AMD’s forthcoming video card I find it prudent to keep expectations in check here, as HBM is just one piece of the complete puzzle that is a GPU. But at the same time let’s be clear here: HBM is the future memory technology of GPUs, there is potential for significant performance increases thanks to the massive increase in memory bandwidth offers, and for roughly the next year AMD is going to be the only GPU vendor offering this technology.

Anandtech
Quote:
Originally Posted by PCPerspective 
We got some with AMD’s Joe Macri, Corporate Vice President and Product CTO, to talk about AMD’s move to HBM and how it will shift the direction of AMD products going forward.

PCPer
Quote:
Originally Posted by Hexus 
HBM is the next major innovation in DRAM memory and in its purest form drastically reduces power consumption and size by stacking DRAM slices on top of one another rather than having them individually placed around the GPU. Such an approach increases the bus width massively, takes away many of the archaic inefficiencies of regular DRAM and, well, is just a good egg from almost any perspective. Let's dive straight in.

Hexus
Quote:
Originally Posted by Bit-Tech 
As graphics processing is inherently power limited, feeding the memory more power means less available watts for the GPU in any given environment, and GDDR5 is now approaching the stage where the power needed to supply the memory bandwidth modern GPUs require is so high that it's not leaving enough for the GPU itself, causing a performance flatline. This is not a new phenomenon; it is predictable, and AMD and its partners have been working on a solution for some seven years now.

Bit-Tech
Quote:
Originally Posted by Techreport 
Macri said the HBM development effort started inside of AMD seven years ago, so not long after GDDR5 was fully baked. He and his team were concerned about the growing proportion of the total PC power budget consumed by memory, and they suspected that memory power consumption would eventually become a limiting factor in overall performance.

Techreport
Quote:
Originally Posted by Guru3D 
AMD briefed press on HBA last week - High Bandwidth Memory, something they started working on roughly seven years ago. This new type of graphics memory is going to change the para-dime in the graphics industry when we are talking about using less power, smaller form factors but most of all increased & scalable memory bandwidth. In this article we'll dig a little deeper into the new technology.

Guru3D
Quote:
Originally Posted by hardocp 
We were lucky enough to get to spend an hour or so with Joe Macri, AMD Vice President and JEDEC Chairman, and discus new High Bandwidth Memory technology.

hardocp
Quote:
Originally Posted by Extremetech 
During its analyst day two weeks ago, AMD confirmed that its next iteration of high-end Radeon cards would adopt High Bandwidth Memory, or HBM. We’ve previously covered HBM’s technical implementation in some depth, but we haven’t had formal acknowledgment from AMD that it would release the technology, or official data on how it compared to GDDR5. Now, we do. and the final figures point to potent performance for the upcoming Radeon.

Extremetech
Quote:
Originally Posted by SA 
AMD is finally talking about HBM today, and SemiAccurate thinks there is a lot of good in the details. Actually High Bandwidth Memory has a lot of good in the overall picture too so lets take a long look at both.

SemiAccurate

If you see more articles now that the NDA for this HBM slide stack is over please do post.

Also it would seem that all of these (or at the very least most of them) sites are saying that the maximum memory capacity is 4GB.
Edited by Alatar - 5/19/15 at 11:02am
 
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post #2 of 208
Yup, 4GB for GEN1 ... unless you dual stack it, which is what AMD is using, but it is unknown if AMD will use a single stack and be limited to 4GB or go with a dual stack and increase the possibility to 8GB. nVidia is skipping GEN1 and going with GEN2 for Pascal, which has a LOT more capacity (upwards of 64GB down the road, but 16GB initially) and double the speed.

Video Cardz
Quote:
1st Gen HBM

Hynix plans to put four DRAM slices over a single base layer. DRAM dies will be connected to each other with vertical channels called through-silicon vias (TSV). Each of those is capable of transmitting 1Gbps, which theoretically should give us 128GB/s of bandwidth. First generation of HBM would offer up to 4 dies per stack.

2nd Gen HBM

Hynix is still developing this technology. The company is currently testing 256 MB slices forming 1GB stacks. Soon, Hynix will start stacking 1GB dies to form 4GB modules. And we are just talking about 4-layer stacks. Nothing, except further research and development, is keeping us away from stacking 8 layers, only this option will only increase the capacity, as bandwidth will be limited to what 4-layers can offer (at least that’s what I’m getting from these slides). Second generation HBM will be available either 4 or 8 layers (forming 4GB or 8GB stacks). The speed per stack will double (256 GB/s).

WCCF
Quote:
4xHBM Gen 1 = 4 GB
3xHBM Gen 1 = 3 GB
2xHBM Gen 1 = 2 GB
1xHBM Gen 1 = 1 GB

4xHBM Gen 2 = 16 GB/32 GB/64 GB
3xHBM Gen 2 = 12 GB/24 GB/48 GB
2xHBM Gen 2 = 8 GB/16 GB/32 GB
1xHBM Gen 2 = 4 GB/8 GB/16 GB

Edited by 47 Knucklehead - 5/19/15 at 6:17am
post #3 of 208
The heck with the slides, what interests me the most is that since AMD co-developed HBM with Hynix, will they get an cut from sales? rolleyes.gif
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post #4 of 208
The new amd cards with this, are they on a new process or the same 28nm?
post #5 of 208
Quote:
Originally Posted by Newbie2009 View Post

The new amd cards with this, are they on a new process or the same 28nm?

3xx on 28nm.
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post #6 of 208
Quote:
Originally Posted by MadRabbit View Post

3xx on 28nm.

Ah that is disappointing.
post #7 of 208
Quote:
Originally Posted by MadRabbit View Post

The heck with the slides, what interests me the most is that since AMD co-developed HBM with Hynix, will they get an cut from sales? rolleyes.gif

Valid question. If so, could very well be a nice money source for AMD. But having said that, IF AMD gets anything, I seriously doubt it will be much, after all it's not like AMD is know for being a memory designer, further, since it is a JEDEC standard. As such, they have to abide by the JEDEC patent standards. So maybe if they get $1 a pop for the patent, I would suspect that AMD would get maybe $0.10 of that. AMD "helped" develop GDDR5 (along with a lot of other companies), so in reality, since HBM will displace GDDR5 eventually, what ever money they get from the HBM patent will offset what they are no longer getting from GDDR5 patent revenues.

HBM really is nothing new, it really was born out of the idea of the Hybrid Memory Cube technology that was developed to be faster than DDR3 and had about a dozen companies developing it. HBM is basically better, so it won.
Edited by 47 Knucklehead - 5/19/15 at 6:39am
post #8 of 208
post #9 of 208
This seems much bigger than GPUs. Lower frequencies are associated with lower latencies. While this isn't super important for GPUs, it is a huge interest to CPUs where latency is one of the biggest problems. A combination of closer RAM (less distance) and lower latencies could cut dozens of cycles off cache misses.

For HSA, this solves the problem of either higher CPU latencies to feed the GPU (eg. PS4) or lower latencies for the CPU and choking the GPU (Xbox one). In addition the presence of the ASIC makes off CPU eDRAM cache more viable (POWER7 has 32MB of eDRAM L3 which helps performance, but is huge risk because it is the same chip).

In the SoC world, saving that much power is enough to get everyone's attention. Popping the four or five main components onto the same underlying ASIC as a bonus could have some appeal as well (the appeal of an even larger SoC, but without the yield reduction.
post #10 of 208
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