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[arstechnica] AMD confirms 4GB limit for first HBM graphics card - Page 3  

post #21 of 50
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Quote:
Originally Posted by MapRef41N93W View Post

4K ultra on a single card is so underwhelming..

Its price to performance ratio is underwhelming compared to the previous gen Titan, which were 50-75% faster than other single card options. A 30% bump over a 980 for the same price as the original Titan is extremely underwhelming, especially considering the Kepler Titans has the FP64 performance to justify the price. $1000 for the Titan X's performance is absurd. They made a card worth $700-800 max and then threw on a ridiculous amount of VRAM to justify the price and name.
Edited by fcman - 5/21/15 at 9:32am
post #22 of 50
since bandwidth is much higher, it has 4x the bandwidth which is comparable to about 12GB of GDDR5
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post #23 of 50
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Originally Posted by 47 Knucklehead View Post

Wrong.

Each level chip int the stack will increase the bus by 1024-bits UP TO A MAX OF 4096-bits. You can't just keep adding more and more chips to get a fatter and fatter pipe. If that were the case, you could just keep adding more and more memory chips and get a 32,768-bit bus or more. rolleyes.gif

GEN1 is limited to 4096-bits wide bus.

As I said, you can add more stacks to increase capacity, but adding more beyond the first stack of 4 will not get you a wider bus.
Reading through some of the material again, I see no such hard-limit on buswidth. Anandtech talks about 2-8 stacks aswell. Could you point me to where it says HBM1 is hardlimited to a 4096 bus? (I thought the differences between gen1 and 2 was the number of slices in each stack.
post #24 of 50
Quote:
Originally Posted by Buris View Post

since bandwidth is much higher, it has 4x the bandwidth which is comparable to about 12GB of GDDR5
Bandwidth is much higher but that doesn't change the capacity. Once this hits the vram wall it will bite the dust just like every other card. Titan X will be better if a game needs more vram since it can go without swapping until the huge 12GB is full. 8GB is however also a lot even for 4K since I have it and I only have 4GB.

Extra bandwidth doesn't make up for capacity the 970 has 4GB and you can use it all still people say it's 3,5 While it's not just because the last 0,5GB is as slow as swapping to ram.
post #25 of 50
Quote:
Originally Posted by Hattifnatten View Post

Reading through some of the material again, I see no such hard-limit on buswidth. Anandtech talks about 2-8 stacks aswell. Could you point me to where it says HBM1 is hardlimited to a 4096 bus? (I thought the differences between gen1 and 2 was the number of slices in each stack.

They Hynix technical data sheets.

http://www.jedec.org/standards-documents/docs/jesd235
post #26 of 50
Quote:
Originally Posted by maarten12100 View Post

Bandwidth is much higher but that doesn't change the capacity. Once this hits the vram wall it will bite the dust just like every other card. Titan X will be better if a game needs more vram since it can go without swapping until the huge 12GB is full. 8GB is however also a lot even for 4K since I have it and I only have 4GB.

Extra bandwidth doesn't make up for capacity the 970 has 4GB and you can use it all still people say it's 3,5 While it's not just because the last 0,5GB is as slow as swapping to ram.

if it is managed well by drivers it doesnt have to be the case. With HBM bandwidth u can swap out unused data much faster. As AMD's rep said, memory b/w was a bottleneck...
post #27 of 50
Quote:
Originally Posted by velocityx View Post

so they gonna hype the dual gpu one as 8 gb because dx12 can combine memory.

Thats was just a rumor. There is no proof that it will combine memory, we have to wait and see.
post #28 of 50
Quote:
Originally Posted by 47 Knucklehead View Post

They Hynix technical data sheets.

http://www.jedec.org/standards-documents/docs/jesd235
Quote:
HIGH BANDWIDTH MEMORY (HBM) DRAM

JESD235

Oct 2013

The HBM DRAM is tightly coupled to the host compute die with a distributed interface. The interface is divided into independent channels. Each channel is completely independent of one another. Channels are not necessarily synchronous to each other. The HBM DRAM uses a wide-interface architecture to achieve high-speed, low-power operation. The HBM DRAM uses differential clock CK_t/CK_c. Commands are registered at the rising edge of CK_t, CK_c. Each channel interface maintains a 128b data bus operating at DDR data rates.

Your reading comprehension is astounding to deduce that HBM Gen 1 is limited to a 4096bit bus from reading that. Go back to uni and read the course you read or smoke whatever you're smoking, hard choice.

Edit: to achieve a 4096bit bus they need to have 32x128 bus and where is the data showing how much each stack amounts to?
Edited by Liranan - 5/21/15 at 10:11am
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post #29 of 50
Quote:
Originally Posted by Liranan View Post


It states clearly that HBM Gen 1 is limited to a 4096bit bus because I just made it up.

I take it you haven't downloaded and read the PDF?
post #30 of 50
Quote:
Originally Posted by 47 Knucklehead View Post

I take it you haven't downloaded and read the PDF?

Please quote the relevant text.

Edit: if it does indeed, unequivocally state the HBM Gen 1 is limited to a 4096bit bus and only 4GB VRAM I will sincerely apologise as it's 01:15 and time for me to sleep.
Edited by Liranan - 5/21/15 at 10:15am
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