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Software for R9 285 bios edit - Page 50

post #491 of 1079
Quote:
Originally Posted by gupsterg View Post

usClockStretchAmount is part of Adaptive Clocking IMO.

Tonga = 03 00 USHORT usClockStretchAmount;

Fiji = 00 00 USHORT usClockStretchAmount;

Polaris 10 XT = 02 00 USHORT usClockStretchAmount;

Thanks for the info thumb.gif

I saw one r9 285 with 00 00 USHORT usClockStretchAmount, I don't know if it is the same value for all of then.

I only see changes on voltages changing usClockStretchAmount from 0 to 3, with 2 I see the same as 3. But I think changin this is causing me black screens.

The only thing I see is changing clock behavior is power efficiency toggle, and this: http://forums.guru3d.com/showthread.php?t=406157

According to your link voltage droops may cause inestability if clock isn't decreased, I don't know if power efficiency off may cause inestability because clock is decreasing less.

The problem is that power efficiency on is giving fps drops, if you don't add the above registry lines or block core droop to 700mhz.

I don't think that this is a PSU 12V line problem, I think it is a power efficincy problem. Blocking clocks voltage droop is always -100mv:



, 12V line readings seems to be wrong. Idle droop at 300/150 clocks is -50mv.

With my old 6850 12V line and core voltage isn't drooping:


Edited by mynm - 10/11/16 at 3:20am
post #492 of 1079
No worries on info smile.gif , a Fiji owner (@Bluezone) pointed the article out to me. As it was an interesting read and better than say the slides we see in launch material I thought be good to share it with you smile.gif .

I reckon when "Adaptive clocking" occurs we may not notice it in software monitoring accurately, reading the article it is a very fast low latency process.
Quote:
The droop detection is very low latency, and takes between 1-3 clock cycles to trigger.

This slide is also part of the Carrizo PR material (similar one used in the realworldtech article).

Warning: Spoiler! (Click to show)


On the slide response time is <1 nano second.

IMO "Adaptive clocking" is different feature to say "Power Efficiency" toggle, the vdroop that the system responds to under "Adaptive clocking" is different also from the variance we see from VID and VDDC due to LLC / EVV.

Your 12V rail being a low read on the 380 may just be down to how software monitoring can differ to DMM reading. I know on my Hawaii cards I never saw 12V in HWiNFO / GPU-Z but if I used a DMM all was AOK. I don't think it is the SW as such but just how the voltage control chip / sense circuits relay information to SW.

Have you checked with DMM 12V at PCI-E plug?
Edited by gupsterg - 8/12/16 at 5:13am
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post #493 of 1079
Ok thanks for the explanation.

But If a 1 nano second droop is a problema, a -100mv drop seems to be a problem as well biggrin.gif.

I don't know if LLC can solve it, the problem is where is it on i2c dump:
Warning: Spoiler! (Click to show)

[ ATI I2C Device GPU #1 / B06-D24 ]

0000 FF 80 17 7F FF FF FF FF FF FF FF FF FF FF FF FF ...............
0010 00 FF FF FF FF FF FF FF FF B0 FF FF FF FF FF FF ................
0020 22 00 FF FF 00 18 A8 FF FF FF FF FF FF FF FF FF "...............
0030 FF FF FF FF FF FF FF FF 01 00 FF FF FF FF FF FF ................
0040 FF FF FF FF FF FF FF FF FF FF 64 FF FF FF FF 55 ..........d....U
0050 FF 46 00 64 FF 10 FF FF FF FF FF FF FF FF FF FF .F.d............
0060 FF FF FF FF FF FF FF FF 2C FF FF FF FF FF FF FF ........,.......
0070 FF FF FF FF FF FF FF FF 00 00 00 00 00 00 FF FF ................
0080 FF FF FF FF FF FF FF FF E9 FF FF 3F F0 00 FF FF ...........?....
0090 FF FF FF FF FF FF 64 FF FF 1A 22 03 FF FF FF FF ......d...".....
00A0 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ................
00B0 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ................
00C0 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ................
00D0 00 01 00 03 50 02 00 FF FF FF 01 FF FF FF FF FF ....P...........
00E0 FF 00 00 02 03 03 00 3D FF FF FF FF FF FF FF FF .......=........
00F0 FF FF FF 68 FF FF FF 0A BC 9C FF 07 FF 0F FF FF ...h............

[ ATI I2C Device GPU #1 / B06-D24 ]

0000 FFFF 2F80 7E17 FF7F FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF
0010 6F00 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 4CB0 FFFF FFFF FFFF FFFF FFFF FFFF
0020 6022 0000 FFFF FFFF 0000 0018 00A8 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF
0030 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 0001 0000 FFFF FFFF FFFF FFFF FFFF FFFF
0040 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 0064 FFFF FFFF FFFF FFFF 0055
0050 FFFF 0046 0000 0064 FFFF 0010 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF
0060 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 012C FFFF FFFF FFFF FFFF FFFF FFFF FFFF
0070 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FB00 0000 2D00 4600 5000 3B00 FFFF FFFF
0080 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF D2E9 FFFF FFFF 013F A2F0 0000 FFFF FFFF
0090 FFFF FFFF FFFF FFFF FFFF FFFF A364 FFFF FFFF 001A 1022 8103 FFFF FFFF FFFF FFFF
00A0 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF
00B0 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF
00C0 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF
00D0 E200 8E01 3400 5603 BA50 2C02 9F00 FFFF FFFF FFFF 6201 FFFF FFFF FFFF FFFF FFFF
00E0 FFFF 6800 D500 B002 A103 CA03 7E00 003D FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF
00F0 FFFF FFFF FFFF 0368 FFFF FFFF FFFF 810A F5BC F29C FFFF 5807 FFFF 1D0F FFFF FFFF

I don't see any info about that, I only see this now thanks to buildzoid: http://forum.hwbot.org/showthread.php?t=157437 , I will see if I can find some thing on NCP81022 datasheet.

I don't have a multimeter, but I have a new PSU so I think that 12v line isn't any problem, and mother board HWinfo64 12v line is ok.

Edited:

Do you think that register E4 is LL slope? biggrin.gif, E6 is offset, E7=3D is Current VID 1.16875V =1.55V- 61*0.00625V.

Acording to datasheet 3 is 011−LL slope 38.7%.

Edited: Ok I think that I had misunderstood how voltage is working because I'm used to constant voltages with 6850.

So 1.16875V is VID

8B 3f=63--> 1.15625V is real voltage, due to LLC / EVV, without load

Voltage is between ~ 1.131v, 1.125v, 1.113v under load with gpuz render test, (I'm now usin 00 LL slope to test), so this is voltage drop with load:



Now I dont see on gaming voltage peaks to more than 1.156v, I think I don't see it because power efficiency off and LL slope to 00, but voltage is droping to 1.063v:




Acording to Adaptive Clocking article more stretche amount is more power saving, that is one of the thinks I see testing usClockStretchAmount.
Whit 00 I see more power consumption than with 03. So it matches, thanks thumb.gif.

Edited: Is it F7 OSC Freq, Vrm switching frequency?, is A=10 and acordin to page 26 table is 400khz.

Edited: Testing 04 LL slope, and I see exactily the same V values, with power efficincy off. I'm using 16.7.2 drivers, In older drivers I see voltage peaks, I don't know why now not.
Edited by mynm - 8/17/16 at 7:32am
post #494 of 1079
+ rep smile.gif , many thanks for share of info / testing data smile.gif .
Quote:
Originally Posted by mynm View Post

I don't see any info about that, I only see this now thanks to buildzoid: http://forum.hwbot.org/showthread.php?t=157437 , I will see if I can find some thing on NCP81022 datasheet.Ok thanks for the explanation.

Thanks for that link and nice of @buildzoid share it. I will read it when have time. I have no experience of the voltage chip employed on your card.
Quote:
Originally Posted by mynm View Post

Do you think that register E4 is LL slope? biggrin.gif, E6 is offset, E7=3D is Current VID 1.6875V =1.55V- 61*0.00625V.

Acording to datasheet 3 is 011−LL slope 38.7%.

E4 is LLC / slope smile.gif , dunno about E6 I think it is D5, E7 yes is current VID. (Will read PDF more in depth when time allows).
Quote:
This register reports back the current VID Code being output incl. Offset being output
Quote:
Originally Posted by mynm View Post

8B 3f=63--> 1.15625V is real voltage, due to LLC / EVV, without load

Yes on LLC / EVV , but would be including GPU under load, if it is under load. As this would technically be VDDC (ie what voltage GPU is getting for the VID being applied).
Quote:
Originally Posted by mynm View Post

Voltage is between ~ 1.131v, 1.125v, 1.113v under load with gpuz render test, (I'm now usin 00 LL slope to test), so this is voltage drop with load:

I'm assuming your thinking this is voltage droop as you had GPU set to higher VID for that DPM? IMO it gets difficult to assess droop with apps we have currently. Ideally we would need an application which is reading back what VID is being requested by GPU, what VDDC it is getting and know if LLC on or off / slope setting.
Quote:
Originally Posted by mynm View Post

Now I dont see on gaming voltage peaks to more than 1.156v, I think I don't see it because power efficiency off and LL slope to 00, but voltage is droping to 1.063v:

I think you are seeing EVV at play there (ie when card is in same DPM state for differing apps and voltage differs due to differing app loading GPU).
Quote:
Originally Posted by mynm View Post

Acording to Adaptive Clocking article more stretche amount is more power saving, that is one of the thinks I see testing usClockStretchAmount.
Whit 00 I see more power consumption than with 03. So it matches, thanks thumb.gif.

Sweet biggrin.gif .
Quote:
Originally Posted by mynm View Post

Edited: Is it F7 OSC Freq, Vrm switching frequency?, is A=10 and acordin to page 26 table is 400khz.

Yes smile.gif , that PDF shared by buildzoid is biblical biggrin.gif . Try setting it to 05h as that should get you 300kHz, which will lower VRM temps but up efficiency and not effect OC ability. The Stilt sets Hawaii ROMs he makes to 300kHz (default is 500kHz).
Quote:
Originally Posted by mynm View Post

Edited: Testing 04 LL slope, and I see exactily the same V values, with power efficincy off. I'm using 16.7.2 drivers, In older drivers I see voltage peaks, I don't know why now not.

Sorry not had or got that card, perhaps another owner may share info with you.
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post #495 of 1079
Quote:
Originally Posted by gupsterg View Post

+ rep smile.gif , many thanks for share of info / testing data smile.gif
Cheers!, you're welcome thumb.gif
Quote:
Originally Posted by gupsterg View Post

dunno about E6 I think it is D5
E6 is offset, it is an Unwinder and AMDMatt share: http://forums.overclockers.co.uk/showpost.php?p=28012664&postcount=41, D5 I have tested to 01 and I don't see changes. D7 is invalid.
Quote:
Originally Posted by gupsterg View Post

Yes on LLC / EVV , but would be including GPU under load, if it is under load. As this would technically be VDDC (ie what voltage GPU is getting for the VID being applied).
I'm assuming your thinking this is voltage droop as you had GPU set to higher VID for that DPM? IMO it gets difficult to assess droop with apps we have currently. Ideally we would need an application which is reading back what VID is being requested by GPU, what VDDC it is getting and know if LLC on or off / slope setting.

I think you are seeing EVV at play there (ie when card is in same DPM state for differing apps and voltage differs due to differing app loading GPU).

I'm using aida64 dumps at stock values, I will try with AB readings under load.
Quote:
Originally Posted by gupsterg View Post

Yes smile.gif , that PDF shared by buildzoid is biblical biggrin.gif . Try setting it to 05h as that should get you 300kHz, which will lower VRM temps but up efficiency and not effect OC ability. The Stilt sets Hawaii ROMs he makes to 300kHz (default is 500kHz).

I will try but I can't know if it is working because I don't have VRM temps readings.
post #496 of 1079
Nice research on voltage offset smile.gif , +rep.

Look forward to reading updates on your endeavours thumb.gif .

I and @Bluezone are about to implement clock stretching on Fiji to see if it a) works b) benefits us.
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post #497 of 1079
Quote:
Originally Posted by gupsterg View Post

Nice research on voltage offset smile.gif , +rep.

Look forward to reading updates on your endeavours thumb.gif .

I and @Bluezone are about to implement clock stretching on Fiji to see if it a) works b) benefits us.

Thanks thumb.gif. Interesting, I will follow Fiji threads to see the progress.

I have tested F7 to 05, is applied, but I don't know how to see if it is working. Less power consumption?, higher amps?, lower core temps?.

About E7 and B8, I have tested readings with AB, with core bloked to 985/1450 with gpu tweak, driver 16.8.2 and power efficiency off.

And I get without load E7= 3d--> 1.16875v VID, B8=3f-->1.15625v vddc:




And with load E7= 3d--> 1.16875v VID, B8=45-->1.11875v vddc:




So, is 1.11875v a v droop?

Edited: Sorry, I think I'm misunderstanding things.

I think that Vdroop is diference between VID 1.6878V and VDDC without load 1.15625V.

And Vdrop is the diference between VDDC 1.15625V and load VDDC in this case 1.11875V.

Am I right?

Edited:

Testings of usClockStretchAmount:

00:




03:



05:



I see diferent max voltages and more power consumption like 00<03<05, temperatures are the same. I don't know if it is only causality y will need more tests.

I have tested with oc to 1100 but I have red screen with 00.

I have tested as well usClockStretchAmount 05 LLS to 7 and sfw to 5 at at stock clocks but I have a freezing, so I don't know how is working it.

I'm having freezes after W10 anniversary update, so I don't know if them are caused by changes on PWP or that. So I can't do more test, until solving the problem. But I think that if imposible to solve..., I will test linux to see if with it problem is solved, and to discard hardware problems, or W7. But I'm tired, so I don't know how long that will take me to do it, biggrin.gif.

If some one ask me to do some test I will do it thumb.gif.

Edited: I see gpu memory erros on one of my screenshots, is the first time I see memory erros, perhaps is gpu memory causing freezes?. I will try to know.

Edited:About loadline, I see at http://media.digikey.com/pdf/Data%20Sheets/ON%20Semiconductor%20PDFs/NCP81022.pdf page 39 about register 0xE4 on tonga NCP81022 that:
Quote:
This register sets the internal loadline attenuation. The max loadline is controlled externally by
setting the gain of the CSA. The max loadline can be adjusted between 0% and 100% of the
external loadline.

Could CSA by Clock Stretch Amount?. So it could be capping LL slope. Or Current Sense Amplifier?.
And perhaps "gain of the CSA" could be 0x38= 0x0001 IOUT_CAL_ GAIN "Sets the ratio of voltage sensed to current output. Scale is Linear and is expressed in 1/Ω". But I don' know how to change it.frown.gif
Edited by mynm - 8/22/16 at 8:32am
post #498 of 1079
I'm chiming in a bit here, just read over some of your posts and various data entries so if I ask something clearly answered already I apologize.

So what have you guys achieved so far? Max truly stable core clock and ram clock?

The R9 380X is pretty neat, I've managed to make it cold to the touch at idle with fans off. It reports about 1/2 watt on the ram and core. Amazing savings from stock idle.

I'm slowly progressing and finding out answers to questions with lots of trial and error.

Primarily TongaBiosReader in the lower dmp control area has the ability to set both core and ram voltage which is troubling.

It's troubling because the ram really should not see more than 10 watts of load or anything above 1225mv and that's at 1563Mhz which is 200GB/s from 192GB/s.

Basically TongaBiosReader doesn't let you set the RAM voltage and the CORE voltage separately.

Has anyone asked the developer of the software about this or how to contact the person?

If I knew exactly which field controlled the CORE, and which the RAM I could fix the problem. Since the ram at high volts makes the whole thing unstable. So it's best to keep ram no more than 1225mv.

While setting the CORE as high as 1450mv...

Below voltages are just rough estimates. Since If I could set the value to control the core only I would know for sure. Since the TongaReader ups the Core & Ram...

R9 380X ...
1000Mhz = 32GPixel @ 1100mv
1032Mhz = 33GPixel @ 1163mv
1063Mhz = 34GPixel @ 1188mv
1094Mhz = 35GPixel @ 1225mv
1125Mhz = 36GPixel @ 1275mv
1157Mhz = 37GPixel @ 1325mv
1188Mhz = 38GPixel @ 1375mv
1219Mhz = 39Gpixel @ 1425mv
1250Mhz = 40GPixel @ 1450mv

Here's stock bios



Here's 1094Mhz core 1563Mhz bios known stable with the massive idle power reduction...

Nevermind 1094Mhz isn't stable anymore because for a while I saw like 1.256v on the core and 1.244v on the ram and now like 1.194v and 1.20v so not stable... TongaBiosReader is pretty useless because I can't affect the heavy 3d volts only idle and fan table... Just wish it could affect heavy 3d volts .. any advice? it doesn't seem to do what the bios says to do...



R9380XStable1094.zip 42k .zip file
Edited by chris89 - 8/28/16 at 1:29pm
post #499 of 1079
Quote:
Originally Posted by mynm View Post


Hi mynm, I see in your pic ATOM BIOS READER, how did you get that app and can you edit the values?

I think that's the answer to pulling off what I need. The ability to leave ram voltage alone, and only up the core voltage to pull off higher clocks on the core.

So far I have pulled off 1094mhz fairly easily, a bit of 1125, and some 1157Mhz. However 1188, 1219, 1250, 1282 aren't possible until I can edit only the core voltage.

Thanks man
post #500 of 1079
Quote:
Originally Posted by chris89 View Post

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I'm chiming in a bit here, just read over some of your posts and various data entries so if I ask something clearly answered already I apologize.

So what have you guys achieved so far? Max truly stable core clock and ram clock?

The R9 380X is pretty neat, I've managed to make it cold to the touch at idle with fans off. It reports about 1/2 watt on the ram and core. Amazing savings from stock idle.

I'm slowly progressing and finding out answers to questions with lots of trial and error.

Primarily TongaBiosReader in the lower dmp control area has the ability to set both core and ram voltage which is troubling.

It's troubling because the ram really should not see more than 10 watts of load or anything above 1225mv and that's at 1563Mhz which is 200GB/s from 192GB/s.

Basically TongaBiosReader doesn't let you set the RAM voltage and the CORE voltage separately.

Has anyone asked the developer of the software about this or how to contact the person?

If I knew exactly which field controlled the CORE, and which the RAM I could fix the problem. Since the ram at high volts makes the whole thing unstable. So it's best to keep ram no more than 1225mv.

While setting the CORE as high as 1450mv...

Below voltages are just rough estimates. Since If I could set the value to control the core only I would know for sure. Since the TongaReader ups the Core & Ram...

R9 380X ...
1000Mhz = 32GPixel @ 1100mv
1032Mhz = 33GPixel @ 1163mv
1063Mhz = 34GPixel @ 1188mv
1094Mhz = 35GPixel @ 1225mv
1125Mhz = 36GPixel @ 1275mv
1157Mhz = 37GPixel @ 1325mv
1188Mhz = 38GPixel @ 1375mv
1219Mhz = 39Gpixel @ 1425mv
1250Mhz = 40GPixel @ 1450mv

Here's stock bios



Here's 1094Mhz core 1563Mhz bios known stable with the massive idle power reduction...

Nevermind 1094Mhz isn't stable anymore because for a while I saw like 1.256v on the core and 1.244v on the ram and now like 1.194v and 1.20v so not stable... TongaBiosReader is pretty useless because I can't affect the heavy 3d volts only idle and fan table... Just wish it could affect heavy 3d volts .. any advice? it doesn't seem to do what the bios says to do...



R9380XStable1094.zip 42k .zip file


Quote:
Originally Posted by chris89 View Post

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Hi mynm, I see in your pic ATOM BIOS READER, how did you get that app and can you edit the values?

I think that's the answer to pulling off what I need. The ability to leave ram voltage alone, and only up the core voltage to pull off higher clocks on the core.

So far I have pulled off 1094mhz fairly easily, a bit of 1125, and some 1157Mhz. However 1188, 1219, 1250, 1282 aren't possible until I can edit only the core voltage.

Thanks man



Memory voltage can't be modified.

Vddci isn't memory voltage.

If you whant to change vddci you don't have to go above 1.2v, or 1.175v, but I think that 1.1v is ok, and it doesn't affect memory OCing.

Max vddci is 50mv less than max vddgfx table2 voltage. If you whant to change it you have to change usVddcOffset at atom_powerplay_sclk_dependency_object_1.

ATOM BIOS READER is only for reading BIOS you can download it here:https://github.com/Hedzin

With ATOM BIOS READER you can see where the value is located on BIOS at table offset column, but you can't mod the value on it, you have to use an hexadecimal editor like HxD https://www.mh-nexus.de/en/

For example If you whant 1.250V for core, vddci will be 1.2V, because usVddcOffset is cdff-->ffcd= -51 calculated with windows calculator with programer mode and in word mode (real offset is always 1mv less). So if you want 1.1V for vddci you have to change it to -151--> ff69-->69ff.

Edited: After moding values with the hexadecimal editor you have to open the bios on TONGA BIOS READER and save it to fix checksum. You can see if it is fixed at overview on checksum control.

If you whant I could mod your bios with the values you whant, and then I will explain how I did it.
Edited by mynm - 8/28/16 at 4:37pm
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