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*Official* Intel DDR4 24/7 Memory Stability Thread - Page 176

post #1751 of 5605
Quote:
Originally Posted by Silent Scone View Post

For a start, he will recieve a bump for setting his refresh interval too high.
You lost me. Do you mean for not setting a high refresh interval? Otherwise I don't understand what the refresh interval does that you mentioned earlier as it doesn't do what you'd think.
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post #1752 of 5605
Quote:
Originally Posted by djgar View Post

OK, I'm totally impressed (and depressed rolleyes.gif) - how did you get such a higher memory benchmark with same # of cores and lower speeds and timings than mine? Out with it! We have ways of making you talk (figuratively speaking of course)! biggrin.gif

Cache speed is actually 4179:

What I did was put RAM on XMP all my sub timings at Auto except 15-15-15-33 1T, set RAM to 2000MHZ in BIOS on 125 strap, reboot, saw the Auto XMP sub timings which will be lower on XMP when using a low RAM speed, manually set the timings as they appeared in Auto, maxed out DRAM Refresh Interval at 32767, it's as high as it goes. Set DRAM REF Cycle Time to 278, Four ACT Win Time (tFAW) to 20 (4X Read To Pre Time), Read To PRE time (tRTP) to 5. Then reboot into BIOS and reset to 3000MHZ. You may have to use a bit higher DRAM REF Cycle Time then 278 and lower DRAM Refresh Interval then 32767 to get stable at 3200MHZ.

If you're using the 100 Strap try it with 2133 RAM speed. if you PC won't boot after doing that, try one RAM speed higher in BIOS and same thing. You want to manually set the sub timings at the settings at the speed your PC boots at, then HCI test for stability overnight. biggrin.gif

Edit: I dunno if it matters but I'm a 5930k and you're a 5820k but it's memory bandwidth so I don't think it really does matter much. redface.gif


Edited by KedarWolf - 7/1/16 at 9:28am
    
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post #1753 of 5605
Thread Starter 
Quote:
Originally Posted by stargate125645 View Post

You lost me. Do you mean for not setting a high refresh interval? Otherwise I don't understand what the refresh interval does that you mentioned earlier as it doesn't do what you'd think.


You're confused, two different things. Refresh internal is tREFI. Although this setting is also best left at the default value, the offset of setting a much higher value at faster frequencies is not worth it as the performance gain is minimal, and in tow you increase the chances of memory corruption as the time between refreshes is longer. It's something that has been covered a few times, as increasing the period between refreshes will make AIDA cache and memory benchmark look a tad more impressive for screenshot flexin'.
Edited by Silent Scone - 7/1/16 at 9:59am
post #1754 of 5605
Quote:
Originally Posted by Silent Scone View Post

Quote:
Originally Posted by stargate125645 View Post

You lost me. Do you mean for not setting a high refresh interval? Otherwise I don't understand what the refresh interval does that you mentioned earlier as it doesn't do what you'd think.


You're confused, two different things. Refresh internal is tREFI. Although this setting is also best left at the default value, the offset of setting a much higher value at faster frequencies is not worth it as the performance gain is minimal, and in tow you increase the chances of memory corruption, as the time between refreshes is longer. It's something that has been covered a few times, as increasing the period between refreshes will make AIDA cache and memory benchmark look a tad more impressive for screenshot flexin'.
Why would setting a refresh interval higher make bandwidth increase, though. That sounds counter-intuitive to me.
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post #1755 of 5605
Thread Starter 
Quote:
Originally Posted by stargate125645 View Post

Why would setting a refresh interval higher make bandwidth increase, though. That sounds counter-intuitive to me.


Because during cell refresh the memory becomes inactive, increasing the interval allows more data to be driven before the next
post #1756 of 5605
Quote:
Originally Posted by KedarWolf View Post

What I did was put RAM on XMP all my sub timings at Auto except 15-15-15-33 1T, set RAM to 2000MHZ in BIOS on 125 strap, reboot, saw the Auto XMP sub timings which will be lower on XMP when using a low RAM speed, manually set the timings as they appeared in Auto, maxed out DRAM Refresh Interval at 32767, it's as high as it goes. Set DRAM REF Cycle Time to 278, Four ACT Win Time (tFAW) to 20 (4X Read To Pre Time), Read To PRE time (tRTP) to 5. Then reboot into BIOS and reset to 3000MHZ. You may have to use a bit higher DRAM REF Cycle Time then 278 and lower DRAM Refresh Interval then 32767 to get stable at 3200MHZ.

If you're using the 100 Strap try it with 2133 RAM speed. if you PC won't boot after doing that, try one RAM speed higher in BIOS and same thing. You want to manually set the sub timings at the settings at the speed your PC boots at, then HCI test for stability overnight. biggrin.gif

Edit: I dunno if it matters but I'm a 5930k and you're a 5820k but it's memory bandwidth so I don't think it really does matter much. redface.gifWarning: Spoiler! (Click to show)

Thanks! I'll check this out when my TZ set comes in. I figured as much for the CPUs, but I'm wondering about the MB making a diff ...
post #1757 of 5605
Quote:
Originally Posted by stargate125645 View Post

Why would setting a refresh interval higher make bandwidth increase, though. That sounds counter-intuitive to me.

The charge stored in a DRAM cell drains away over time. Therefore, the charge level within a cell must be maintained by refreshing the memory periodically. During the process of a refresh, the memory is not available for a read or write until the refresh is completed. By increasing tREFI, the time in which all banks must be refreshed is larger, which allows more read/write transactions to take place, hence the higher bandwidth. Of course, increasing this value too far can result in the stored charge falling below VREF. If that happens, a logic 1, becomes a 0, which is corrupt data.
post #1758 of 5605
Quote:
Originally Posted by Raja@ASUS View Post

The charge stored in a DRAM cell drains away over time. Therefore, the charge level within a cell must be maintained by refreshing the memory periodically. During the process of a refresh, the memory is not available for a read or write until the refresh is completed. By increasing tREFI, the time in which all banks must be refreshed is larger, which allows more read/write transactions to take place, hence the higher bandwidth. Of course, increasing this value too far can result in the stored charge falling below VREF. If that happens, a logic 1, becomes a 0, which is corrupt data.

Thanks for the excellent insight, Raja. I believe I'll leave the refresh time alone and not tempt fate smile.gif
post #1759 of 5605
Quote:
Originally Posted by Raja@ASUS View Post

The charge stored in a DRAM cell drains away over time. Therefore, the charge level within a cell must be maintained by refreshing the memory periodically. During the process of a refresh, the memory is not available for a read or write until the refresh is completed. By increasing tREFI, the time in which all banks must be refreshed is larger, which allows more read/write transactions to take place, hence the higher bandwidth. Of course, increasing this value too far can result in the stored charge falling below VREF. If that happens, a logic 1, becomes a 0, which is corrupt data.

thumb.gif

What do you think of using a ram disk as a way to check if increasing tREFI is over the top? I've been running 22066 which is lees than double the Auto value (~ 12000). Ram disk has been okay for a couple of days (the extent of need that I had at the time). Still, no really clear way to test this?
Edited by Jpmboy - 7/1/16 at 3:59pm
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post #1760 of 5605
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Edited by Jpmboy - 7/1/16 at 3:56pm
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