Originally Posted by Raja@ASUS
JPM has mentioned a few times he feels the IMC is the limiting factor of his memory clocks. I was referencing his wall for memory frequency, not the IMC. Remember the IMC is also responsible for memory frequency... The Edition 10 has a layout optimized for BW-E, so should help him on the memory side in comparison to the R5E.
So far with each of my kits the R5E is behaving better with the BW-E than HW-E. I had 3 HW-E chips in this MB at various times, all behaved similarly which is to say they could run at 2800, 2800 or 2800... I did eventually get 3200 with 1/2 my 128G kit in a benching setup with HW-E, but not something that would pass an hour of stressapp.
So, it appears the OC socket is dead for BW-E as it relates to unicore frequencies owing to BW-E cache architecture.
Pretty fascinating/sad that we are getting to quad-pumped 12GHz effective DDR technology-wise (GDDR5x) Where intel is running a 2.8GHz on-chip cache... and yes I know latency, burst, access vs cache-line on-chip and DDR vs GDDR is a different beast, but still 11-12 vs 2.8-3.7 is a BIG difference.