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*Official* Intel DDR4 24/7 Memory Stability Thread - Page 194

post #1931 of 5485
Quote:
Originally Posted by Desolutional View Post

This is what I've managed to get now, haven't touched the Tertiary timings, just tRFC and tREFI

Interleaving those extra ranks is definitely giving you a substantial read advantage over my four lower density sticks.

This is what I'm getting with my new settings (GSAT stable, btw) that feature extensive secondary and tertiary tuning:

12229209

12229208

12229207
Quote:
Originally Posted by Desolutional View Post

what other timings will help with High Density, Double Sided DIMMs?

The same ones that help any memory, which is most of them, but there are some that can probably leverage your greater memory parallelism better than others.

See how far you can tighten your IOLs before you run into issues. Note that this as much a memory controller timing as a memory timing, so it may not respond much to things like VDIMM, but could respond to VCCSA and/or VCCIO.

I'm not sure how many bank groups your DIMMs have, but any timing with a _L in it generally refers to the delay for the "long" group and reducing these parameters can improve performance where there is frequent bank switching. TCCD_L is generally the most important of these.

Tightening those tertiary timings that end in DR (different row) or DD (different DIMM), which is most of them really, will help more the more DIMMs per channel and the more rows per IC you have. Many of the tertiaries can be tightened quite a bit on most DIMMs/ICs, especially at lower frequences (I can usually run everything except tWRSR at 1 up to about 2133 on DDR3 and ~2800 ish on DDR4).

Really though, it's a ton of trial, error and testing to discover what's worth changing and what's not, then making sure you're still stable.
Quote:
Originally Posted by DarkIdeals View Post

remember not so long ago the "experts" were saying that it would take DDR4 4266mhz or faster RAM to match ~DDR3 2133mhz C10 kits; but here we are slightly beating DDR3 2133 C10 with only DDR4 3200 C13-14 etc..

DDR4 is typically a little faster at similar timings due to bank groups and some other enhancements.

I'm running 2667 CL12 and it kicks the snot out of the DDR3-2133 CL9 I was using with my SB-E/Ivy-E, even at lower uncore clocks...though some of that could be due to HW-E's memory controller. Though I don't personally have any desktop Skylake systems, tests with them show similar trends...DDR3 needs to be run tighter to match DDR4 at the same clocks.
Edited by Blameless - 7/11/16 at 7:28pm
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post #1932 of 5485
Quote:
Originally Posted by DarkIdeals View Post

Kinda wondering about risking two kits of 16GB 3200 C14 but I know rampage boards are iffy with 8 DIMMs active at times.
The bigger risk there isn't the 8 slots. It can handle that, but mixing kits is asking for trouble. It might work if you are ready to tweak and they are close enough, but there is ZERO guarantee that it will and virtual certainty that it might cause you problems or require getting down and dirty with timing and loosen things up even from stock settings. The closer the kits are in characteristics, timing, die rev, etc... the more likely there is a working solution.

Short version: "run away" unless you like science projects. 8 dimms works just fine with SA adjusted as required.

FWIW, I have an X99Pro and a RVE with 8dimms. The X99Pro is actually 2 32G kits of (both 3000, one CAS14, one CAS15) (I ran that in the RVE briefly and then it moved to the X99). The RVE is an 8DIMM kit binned from the GSkill. Both run fine, I've not looked at Aida memory numbers and can't do so right now. However... see above.
Edited by cekim - 7/11/16 at 9:04pm
post #1933 of 5485
Thread Starter 
Quote:
Originally Posted by vibraslap View Post

FWIW I'm able to run my TridentZ at sticker speeds on my overclocked 6900k. 3200MHz 14-14-14-34 CR2 @ 1.35V, 1.0 SA, 4.3GHz 100MHz BCLK, 1.325V on the cpu. I haven't even messed with them much beyond confirming they are stable at sticker speeds on this overclock, so tighter timings could be attainable. I'd like to get mine down to CR1, but that seems far fetched based on what others here have said/experienced.


Is it?
post #1934 of 5485
Thread Starter 
Quote:
Originally Posted by Blameless View Post

Interleaving those extra ranks is definitely giving you a substantial read advantage over my four lower density sticks.

This is what I'm getting with my new settings (GSAT stable, btw) that feature extensive secondary and tertiary tuning:

12229209

12229208

12229207Warning: Spoiler! (Click to show)
The same ones that help any memory, which is most of them, but there are some that can probably leverage your greater memory parallelism better than others.

See how far you can tighten your IOLs before you run into issues. Note that this as much a memory controller timing as a memory timing, so it may not respond much to things like VDIMM, but could respond to VCCSA and/or VCCIO.

I'm not sure how many bank groups your DIMMs have, but any timing with a _L in it generally refers to the delay for the "long" group and reducing these parameters can improve performance where there is frequent bank switching. TCCD_L is generally the most important of these.

Tightening those tertiary timings that end in DR (different row) or DD (different DIMM), which is most of them really, will help more the more DIMMs per channel and the more rows per IC you have. Many of the tertiaries can be tightened quite a bit on most DIMMs/ICs, especially at lower frequences (I can usually run everything except tWRSR at 1 up to about 2133 on DDR3 and ~2800 ish on DDR4).

Really though, it's a ton of trial, error and testing to discover what's worth changing and what's not, then making sure you're still stable.
DDR4 is typically a little faster at similar timings due to bank groups and some other enhancements.

I'm running 2667 CL12 and it kicks the snot out of the DDR3-2133 CL9 I was using with my SB-E/Ivy-E, even at lower uncore clocks...though some of that could be due to HW-E's memory controller. Though I don't personally have any desktop Skylake systems, tests with them show similar trends...DDR3 needs to be run tighter to match DDR4 at the same clocks
.


Interesting tRRD settings, care to explain?
post #1935 of 5485
Quote:
Originally Posted by Silent Scone View Post

Interesting tRRD settings, care to explain?

I can run TRRD/TFAW as low as 1/4 without any apparent stability issues, but there is no performance difference, in anything I can find, below 2/8.

TRRD_L is 4 because I was testing different firmware versions and entering the timings from memory and forgot to set it to 2 when at the time I was taking these screen shots. I'd still use tFAW 8 even if tRRD_L of 4 was necessary as it's a cap on the lower end of the setting; it won't hurt anything if the L bank timings need to be used, but might help if there are several S bank accesses sequentially.
Edited by Blameless - 7/12/16 at 4:47am
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post #1936 of 5485
Quote:
Originally Posted by Blameless View Post

I can run TRRD/TFAW as low as 1/4 without any apparent stability issues

Hello

Should read "I can input settings". This is a case of the motherboard being smarter than the user.
post #1937 of 5485
Quote:
Originally Posted by djgar View Post

Sure, with 10 vs. 8 cores - that's cheating biggrin.gifthumb.gif
.. but of course, why else get a BWE? wink.gif
Quote:
Originally Posted by Blameless View Post

Interleaving those extra ranks is definitely giving you a substantial read advantage over my four lower density sticks.

This is what I'm getting with my new settings (GSAT stable, btw) that feature extensive secondary and tertiary tuning: Warning: Spoiler! (Click to show)
12229209

12229208

12229207
The same ones that help any memory, which is most of them, but there are some that can probably leverage your greater memory parallelism better than others.

See how far you can tighten your IOLs before you run into issues. Note that this as much a memory controller timing as a memory timing, so it may not respond much to things like VDIMM, but could respond to VCCSA and/or VCCIO.

I'm not sure how many bank groups your DIMMs have, but any timing with a _L in it generally refers to the delay for the "long" group and reducing these parameters can improve performance where there is frequent bank switching. TCCD_L is generally the most important of these.

Tightening those tertiary timings that end in DR (different row) or DD (different DIMM), which is most of them really, will help more the more DIMMs per channel and the more rows per IC you have. Many of the tertiaries can be tightened quite a bit on most DIMMs/ICs, especially at lower frequences (I can usually run everything except tWRSR at 1 up to about 2133 on DDR3 and ~2800 ish on DDR4).

Really though, it's a ton of trial, error and testing to discover what's worth changing and what's not, then making sure you're still stable.
DDR4 is typically a little faster at similar timings due to bank groups and some other enhancements.

I'm running 2667 CL12 and it kicks the snot out of the DDR3-2133 CL9 I was using with my SB-E/Ivy-E, even at lower uncore clocks...though some of that could be due to HW-E's memory controller. Though I don't personally have any desktop Skylake systems, tests with them show similar trends...DDR3 needs to be run tighter to match DDR4 at the same clocks.
tRTP 3 - amazing with DDR4
Quote:
Originally Posted by Silent Scone View Post

[/B]

Is it?
Right - there is so much bad info floating around... or folks don't know how to ask a question without trying to be provocative, quoting rumor of just plan wrong "facts". "Everyone is entitled to their own opinion... but not their own facts".
Quote:
Originally Posted by Praz View Post

Hello

Should read "I can input settings". This is a case of the motherboard being smarter than the user.
so Praz, where can we get our (my?) grubby fingers on the chipset minimums for the timings we have access to in Bios?
Edited by Jpmboy - 7/12/16 at 6:13am
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post #1938 of 5485
Quote:
Originally Posted by Praz View Post

Hello

Should read "I can input settings". This is a case of the motherboard being smarter than the user.

I can bench a difference between tRRD 2 and 4.

I don't know if TRRD 1 is actually doing anything, but 2 and 3 do. It's subtle, but it's consistently there in things like WinRAR which is extremely sensitive to memory latency.
Edited by Blameless - 7/12/16 at 5:34am
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post #1939 of 5485
Quote:
Originally Posted by Blameless View Post

I can bench a difference between tRRD 2 and 4.

I don't know if TRRD 1 is actually doing anything, but 2 certainly is.


At the chipset level, 4 is the minimum spacing for tRRD as each burst is 4 clocks. You can't send an ACT while the DQ lines are still toggling. Most of the time, the lower values are available in firmware as the bits are open which reverts to the minimum spacing or incurs a penalty due to a collision. Occasionally, Intel uses an offset.

tRRD_L has no tFAW, as there is no situation where there would be 4 concurrent ACTs to the same bank group.
post #1940 of 5485
All I really know is that tRRD 2 has been producing better results in WinRAR's bench, which is extremely consistent on a stripped down system (sub 0.1% deviation between runs).

I'll set the tRRD values back to 4 and tFAW back to 16 to triple check. It's possible I adjusted something I didn't mean to when originally benching timing changes or that the board is changing things itself.

Gigabyte has a nasty habit of having their memory timing settings change things they aren't supposed to or be outright mislabeled in their beta (and sometimes release) firmware, so I have to check timing configurator, memtweakit, or AIDA64 to make sure of them.
Quote:
Originally Posted by Raja@ASUS View Post

At the chipset level, 4 is the minimum spacing for tRRD as each burst is 4 clocks.

What about burst chops? Can't those still be one or two clocks long? Or do those still require the same 4 cycles and just truncate the transfer?

Wouldn't interleaving allow bursts to be staggered anyway?
Quote:
Originally Posted by Raja@ASUS View Post

tRRD_L has no tFAW, as there is no situation where there would be 4 concurrent ACTs to the same bank group.

I was not aware of this. Have a link to anything with more detail on DDR4's bank groups that includes this information?
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