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*Official* Intel DDR4 24/7 Memory Stability Thread - Page 199

post #1981 of 5477
Quote:
Originally Posted by Jpmboy View Post

@djgar okay. thanks.

Starting with the Timings#1 tab...

  1. Cycle time -> 450, then -> 350 if stable (328 should be possible).
  2. tRAS = CL+tRCD+tRTP. you have it set too low.
  3. tFAW = 4x tRRD (at least). the key here is to get tRTP down to 4 if possible.

All tightening like this costs voltage. you may have to increase VDIMM to as much as 1.45V which looks to be fine for these TZ 3200c14 kits. the Ripjaws 3200c14s work the same, well of course depending on several silicon lottery wins. (ram ICs, IMC.. etc). redface.gif erm... I think you have the 3200c14s??

here's 64GB (yes - 2T). IOLs are a little lower for these.
Warning: Spoiler! (Click to show)

Yes, the 3200c14 Ripjaws. Thank you! I'll experiment! thumb.gif
post #1982 of 5477
Quote:
Originally Posted by Jpmboy View Post

yup, I know... does not work on the R5E-10. fine for the R5E tho.
lol -
Does Version 3.0.5 work?
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post #1983 of 5477
Thread Starter 
Quote:
Originally Posted by Praz View Post

Hello

A couple of G.Skill 3600MHz CAS15 kits. Memory voltage - 1.35.


Praz---R5E10-i7 6950X @ 4.2/3.5---3400MHz-32GB-C14-14-14-36-1T----CPU 1.256V---SA 0.976V---VCCIN 1.824V---HCI 635%---GSAT 2 Hours






Thanks, nice result. Straight 14s on the kit I have here seems to topple over the limit at this frequency with reduced sub timings (within 1.5v)


Will add all results this evening
post #1984 of 5477
Quote:
Originally Posted by lilchronic View Post

Does Version 3.0.5 work?
yeah, tried that first... no go. sad-smiley-002.gif
i keep checking the asrock website for an update...
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post #1985 of 5477
Quote:
Originally Posted by Jpmboy View Post

@djgar okay. thanks.

Starting with the Timings#1 tab...

  1. Cycle time -> 450, then -> 350 if stable (328 should be possible).
  2. tRAS = CL+tRCD+tRTP. you have it set too low.
  3. tFAW = 4x tRRD (at least). the key here is to get tRTP down to 4 if possible.

All tightening like this costs voltage. you may have to increase VDIMM to as much as 1.45V which looks to be fine for these TZ 3200c14 kits. the Ripjaws 3200c14s work the same, well of course depending on several silicon lottery wins. (ram ICs, IMC.. etc). redface.gif erm... I think you have the 3200c14s??

here's 64GB (yes - 2T). IOLs are a little lower for these. Warning: Spoiler! (Click to show)

OK, I got noticeable improvement from ref cycle time = 360, tFAW = 28 and tRAS=41 (tRTP is still 12 on auto). I did an 80 minute GSAT with no problems.

My question on your comment "the key here is to get tRTP down to 4 if possible" is should that happen on auto based on what the other timings male it, or should I try to manually get it stable as close to 4 as possible?

Thanks again! That was really helpful thumb.gif
post #1986 of 5477
Thread Starter 
Quote:
Originally Posted by djgar View Post

OK, I got noticeable improvement from ref cycle time = 360, tFAW = 28 and tRAS=41 (tRTP is still 12 on auto). I did an 80 minute GSAT with no problems.

My question on your comment "the key here is to get tRTP down to 4 if possible" is should that happen on auto based on what the other timings male it, or should I try to manually get it stable as close to 4 as possible?

Thanks again! That was really helpful thumb.gif

The timings won't scale that way, no. You'll have to set it manually. If the board scaled to the minimum values on it's own, most people would struggle to pass POST stress tests
post #1987 of 5477
Quote:
Originally Posted by Silent Scone View Post

The timings won't scale that way, no. You'll have to set it manually. If the board scaled to the minimum values on it's own, most people would struggle to pass POST stress tests

Thanks! I'll see what I can get to pass 80 min. GSAT thumb.gif
post #1988 of 5477
Quote:
Originally Posted by Jpmboy View Post

@djgar okay. thanks.

Starting with the Timings#1 tab...

  1. Cycle time -> 450, then -> 350 if stable (328 should be possible).
  2. tRAS = CL+tRCD+tRTP. you have it set too low.
  3. tFAW = 4x tRRD (at least). the key here is to get tRTP down to 4 if possible.

All tightening like this costs voltage. you may have to increase VDIMM to as much as 1.45V which looks to be fine for these TZ 3200c14 kits. the Ripjaws 3200c14s work the same, well of course depending on several silicon lottery wins. (ram ICs, IMC.. etc). redface.gif erm... I think you have the 3200c14s??
...

Quote:
Originally Posted by Silent Scone View Post

The timings won't scale that way, no. You'll have to set it manually. If the board scaled to the minimum values on it's own, most people would struggle to pass POST stress tests

Thanks for all the help. OK, here's my latest based on:
  • 330 ref cycle time
  • 6 tRRD
  • 4 tRTP
  • 24 tFAW
  • 28 tRAS (yes, not following rule but seems to render slightly better benchmark smile.gif )

This passed 80 mins. GSAT.

post #1989 of 5477
Quote:
Originally Posted by djgar View Post


Thanks for all the help. OK, here's my latest based on:
  • 330 ref cycle time
  • 6 tRRD
  • 4 tRTP
  • 24 tFAW
  • 28 tRAS (yes, not following rule but seems to render slightly better benchmark smile.gif )

This passed 80 mins. GSAT.
Warning: Spoiler! (Click to show)
Nice! thumb.gif
tRAS seems to be tolerant of a -2 vs the calc min window... maybe Intel has applied an offset in the microcode?
noiw gewt in there and set the dram clock to 13, and lower the three timings I flagged below until stability or "productivity" is lost. Some kits can run these at the same value... some work best with a stagger.
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post #1990 of 5477
I'm trying my new 5960x at 4.6GHZ 1.225v, cache at 4.4GHZ at 1.2v, 8x4GB G.Skill 3000 at 3200MHZ 15-16-16-35 1T at 1.4v while I'm at work 10 hours with HCI, I think I have a really good chip. biggrin.gif

No errors at 100% before I left. smile.gif
    
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