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*Official* Intel DDR4 24/7 Memory Stability Thread - Page 215

post #2141 of 5593
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Originally Posted by cekim View Post

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Originally Posted by Jpmboy View Post

I think mine was binned at 4T with 2T being an overclock. redface.gif
4T? What sort of madness is that... I would challenge them to a duel.
Quote:
Originally Posted by stargate125645 View Post

Seems to me the RAM is not operating at its stated specifications, then, like mine.
Takes 2 to tango, compensating for the HWE IMC's limitations at these speeds is the norm.
It didn't run at 1.4V. If I get it to run at stock settings and 1.45V, I should be satisfied? I can test again when I get home. However, I don't understand how giving voltage to the RAM has anything to do with the IMC, which would see none of that voltage. Increasing the cache voltage or system agent voltage or I/O voltage would make more sense (and those voltages are pretty well maxed out and everything is stable, aside from the RAM).
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post #2142 of 5593
^ two options:

buy a known good cpu that can handle 3200C13/14
  • then test your existing ram kit again

buy a known good ram kit that can handle 3200C13/14

Now isolate and figure out where your problem lies.
post #2143 of 5593
Quote:
Originally Posted by sexpot View Post

^ two options:

buy a known good cpu that can handle 3200C13/14
  • then test your existing ram kit again

buy a known good ram kit that can handle 3200C13/14

Now isolate and figure out where your problem lies.
Ostensibly I already did option 2, which can only be confirmed by doing an RMA. Unless someone can explain to me what the RAM voltage has to do with the IMC, it looks like that's my direction. My CPU is doing 4.6GHz core at 1.23V...seems like not a smart move to get rid of that.

Edit: If someone has 32GB of quad channel (really just 4 sticks that will operate at the same level) RAM that operates at 3200C13 guaranteed (guaranteed as in you had it running at that level, not that I will be able to do so), I may be interested. I don't want to buy a brand new set, though, as I'd just RMA the ones I have in that case.
Edited by stargate125645 - 7/20/16 at 10:14am
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post #2144 of 5593
Quote:
Originally Posted by stargate125645 View Post

Ostensibly I already did option 2, which can only be confirmed by doing an RMA. Unless someone can explain to me what the RAM voltage has to do with the IMC, it looks like that's my direction. My CPU is doing 4.6GHz core at 1.23V...seems like not a smart move to get rid of that.
The IMC has to receive the data from the RAM in a read and send it in a write.

The internal function of the CPU and the DRAM is very different:
- DRAM cell is something like a capacitor that gets drained and re-filled when read or refreshed and filled/drained when written as required for 0/1
- CPU is a network of switches and static ram

So, they have different features that dominate when it comes to how fast they can switch/sense outputs/inputs respectively. They will both generally have driver/receiver buffers at the pins (pushing digital logic over PCBs is quite a bit harder than on the chip), but the failure can occur anywhere in the system - a good core OC does not guarantee a good IMC OC in any way shape or form.

HOWEVER, at the pins of the IMC, they have to "agree". Raja has some excellent write-ups with diagrams, but in any digitial system the voltage will swing high or low to some agreed upon voltage representing 0 and 1. A "driver" will generally swing beyond the bare minimum (swinging lower than required for "low" and higher than required for "high"). The receiver of that driver will "sense" "low" or "high" at the agreed upon levels.

As long as all this switching happens within the margins of error, then it all works. BOTH sides of this arrangement are driving and sensing on various pins for a the various phases of the DRAM access for a read or write operation.

So, if the IMC has a lower analog frequency response (higher capacitance for example), the DRAM may switch from "low" to "high" but the IMC may not "sense" this transition fast enough because it is literally low-pass filtering the DRAM's output signal. Same goes for the other direction, the IMC's switch from "low" to "high" or "high" to "low" may not go far enough or fast enough for the DRAM to "sense" it correctly. These transitions also "bounce", "ring" and "overshoot", so it may not even be how fast, but how much slop there is in the signal.

You can compensate on either side of this communication in many circumstances with more current/voltage or more wait-states (CAS, RAS, etc... ). How much you can compensate depends on why it is failing and the inherent frequency response of the circuit.
Edited by cekim - 7/20/16 at 10:32am
post #2145 of 5593
Quote:
Originally Posted by cekim View Post

Quote:
Originally Posted by stargate125645 View Post

Ostensibly I already did option 2, which can only be confirmed by doing an RMA. Unless someone can explain to me what the RAM voltage has to do with the IMC, it looks like that's my direction. My CPU is doing 4.6GHz core at 1.23V...seems like not a smart move to get rid of that.
The IMC has to receive the data from the RAM in a read and send it in a write.

The internal function of the CPU and the DRAM is very different:
- DRAM cell is something like a capacitor that gets drained and re-filled when read or refreshed and filled/drained when written as required for 0/1
- CPU is a network of switches and static ram

So, they have different features that dominate when it comes to how fast they can switch/sense outputs/inputs respectively.

HOWEVER, at the pins of the IMC, they have to "agree". Raja has some excellent write-ups with diagrams, but in any digitial system the voltage will swing high or low to some agreed upon voltage representing 0 and 1. A "driver" will generally swing beyond the bare minimum (swinging lower than required for "low" and higher than required for "high"). The receiver of that driver will "sense" "low" or "high" at the agreed upon levels.

As long as all this switching happens within the margins of error, then it all works. BOTH sides of this arrangement are driving and sensing on various pins for a the various phases of the DRAM access for a read or write operation.

So, if the IMC has a lower analog frequency response (higher capacitance for example), the DRAM may switch from "low" to "high" but the IMC may not "sense" this transition fast enough because it is literally low-pass filtering the DRAM's output signal. Same goes for the other direction, the IMC's switch from "low" to "high" or "high" to "low" may not go far enough or fast enough for the DRAM to "sense" it correctly. These transitions also "bounce", "ring" and "overshoot", so it may not even be how fast, but how much slop there is in the signal.

You can compensate on either side of this communication in many circumstances with more current/voltage or more wait-states (CAS, RAS, etc... ). How much you can compensate depends on why it is failing and the inherent frequency response of the circuit.
So, the signal may not be strong enough when sent from the RAM, in short, unless I up the voltage? If so, that makes sense.
Edited by stargate125645 - 7/20/16 at 10:37am
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post #2146 of 5593
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Originally Posted by stargate125645 View Post

So, the signal may not be strong enough when sent from the RAM, in short, unless I up the voltage? If so, that makes sense.
In short yes, by increasing the voltage at the DIMM, you can potentially overcome the IMC's deaf ear to your RAM's output and/or the amplification of the IMC's output coming to the DIMM (a "buffer" on the I/O is an amplifier) might increase the signal enough that the chips on the DIMM can overcome the weak signal from the IMC.
post #2147 of 5593
Quote:
Originally Posted by cekim View Post

Quote:
Originally Posted by stargate125645 View Post

So, the signal may not be strong enough when sent from the RAM, in short, unless I up the voltage? If so, that makes sense.
In short yes, by increasing the voltage at the DIMM, you can potentially overcome the IMC's deaf ear to your RAM's output and/or the amplification of the IMC's output coming to the DIMM (a "buffer" on the I/O is an amplifier) might increase the signal enough that the chips on the DIMM can overcome the weak signal from the IMC.
OK, then. Just so I have a gameplan going forward: What if 1.45V doesn't work with CL14? Since I've tested a low cache frequency to no avail, the RAM should be the focus given the CPU and cache are stable at my signature speeds, right? Suppose I have to do 1.45V and CL15 or CL16 at 3200MHz. Would I call the RAM bad then? Where is the line to draw where I can be reasonably sure my IMC is just not a picky SOB and the RAM is actually bad?
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post #2148 of 5593
Quote:
Originally Posted by stargate125645 View Post

OK, then. Just so I have a gameplan going forward: What if 1.45V doesn't work with CL14? Since I've tested a low cache frequency to no avail, the RAM should be the focus given the CPU and cache are stable at my signature speeds, right? Suppose I have to do 1.45V and CL15 or CL16 at 3200MHz. Would I call the RAM bad then? Where is the line to draw where I can be reasonably sure my IMC is just not a picky SOB and the RAM is actually bad?
Unless you have equipment to test the ram in isolation, I'm afraid there is no hard line.

If the ram functions at 2133 with no errors, then odds are that the sticker values are what the DIMM manufacturer got on their tester which is supposedly representative of a correctly functioning chip. That's about as good as I've ever been able to say a DIMM was or was not "bad" and then its up to your retailer/provider and their RMA policy. If you churn through multiple kits and get similar results, then that's the answer...

In terms of core/cache OC, they provide "hints", but not certainty. Every one of those billions of gates on the chip has to agree to run "faster" than Intel's markings or you will get an error from whichever part did not.

All the usual techniques for memory apply - more uncore, more sa, more vdimm, tweak timings, etc... wash, rinse and permute... Don't forget to test the lower voltages as well. Too much can hurt as much as too little. Sorry, I don't have any magic bullets, just many hours of "entertainment" wink.gif trying to tease out the best settings.
Edited by cekim - 7/20/16 at 11:04am
post #2149 of 5593
Quote:
Originally Posted by stargate125645 View Post

Edit: If someone has 32GB of quad channel (really just 4 sticks that will operate at the same level) RAM that operates at 3200C13 guaranteed (guaranteed as in you had it running at that level, not that I will be able to do so), I may be interested. I don't want to buy a brand new set, though, as I'd just RMA the ones I have in that case.

Hello

I have set that will do this easily. However none for sale. And I would never guarantee you would be able to run any memory at the same timings/voltage I have. smile.gif
post #2150 of 5593
Only thing left to tweak is RAM stuff, since cache and core aren't stable below current voltages and RAM still won't work at stock even with lower cache speed, I'd think.

Edit: VCCIO and VCCSA I can probably fiddle with a little bit (I can only lower the latter, though). What sort of voltage increments should I test things at when finding the "sweet spot"? Does the number of errors MemTest gives indicate how close I am to being stable such that I can fiddle with the voltages to zone in on the "sweet spot"? Otherwise, it's just guess and check.
Quote:
Originally Posted by Praz View Post

Quote:
Originally Posted by stargate125645 View Post

Edit: If someone has 32GB of quad channel (really just 4 sticks that will operate at the same level) RAM that operates at 3200C13 guaranteed (guaranteed as in you had it running at that level, not that I will be able to do so), I may be interested. I don't want to buy a brand new set, though, as I'd just RMA the ones I have in that case.

Hello

I have set that will do this easily. However none for sale. And I would never guarantee you would be able to run any memory at the same timings/voltage I have. smile.gif
OK...
Edited by stargate125645 - 7/20/16 at 11:53am
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