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*Official* Intel DDR4 24/7 Memory Stability Thread - Page 434

post #4331 of 4441
How come with my newest OC setup (4.4, cache 37, default ram 3200 cl14) it tooks 7-8h for a 1000% coverage in Hci 5.0 (14x2048 Mb)?
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post #4332 of 4441
Larger RAM per instance = longer test with same coverage.
post #4333 of 4441
Can anyone tell me that this is memory instability or cache relate ? 1 error at 330% Thanks in advance.

VCORE 1.365V set 1.344V actual
VCCIO 1.225V set 1.248V actual
VCCSA 1.275V set 1.296V actual
VDIMM 1.45V set 1.48V actual

post #4334 of 4441
Quote:
Originally Posted by Enterprise24 View Post

Can anyone tell me that this is memory instability or cache relate ? 1 error at 330% Thanks in advance.

VCORE 1.365V set 1.344V actual
VCCIO 1.225V set 1.248V actual
VCCSA 1.275V set 1.296V actual
VDIMM 1.45V set 1.48V actual


Was getting the same with my settup..for me it was more VDIMM needed. and / or a combination of to much / not enough V on VCCCSA / VCCIO
Go back a couple of pages and see my initial post where I got 1 error than the last post where I submitted my entry and see the differences.

At work at the moment and can't really go back and check them myself rolleyes.gif
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post #4335 of 4441
Quote:
Originally Posted by Enterprise24 View Post

Can anyone tell me that this is memory instability or cache relate ? 1 error at 330% Thanks in advance.

VCORE 1.365V set 1.344V actual
VCCIO 1.225V set 1.248V actual
VCCSA 1.275V set 1.296V actual
VDIMM 1.45V set 1.48V actual

Set Twr and Tfaw to 24 and see if you can get that stable first. You can then work on lowering them after if your anal about it.
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post #4336 of 4441
Quote:
Originally Posted by becks View Post

Was getting the same with my settup..for me it was more VDIMM needed. and / or a combination of to much / not enough V on VCCCSA / VCCIO
Go back a couple of pages and see my initial post where I got 1 error than the last post where I submitted my entry and see the differences.

At work at the moment and can't really go back and check them myself rolleyes.gif

Thanks I just try more vdimm. If it still fail will try adjust io/sa later.
post #4337 of 4441
Quote:
Originally Posted by Enterprise24 View Post

Can anyone tell me that this is memory instability or cache relate ? 1 error at 330% Thanks in advance.

VCORE 1.365V set 1.344V actual
VCCIO 1.225V set 1.248V actual
VCCSA 1.275V set 1.296V actual
VDIMM 1.45V set 1.48V actual


I, before giving a notch more of vdimm, would try to relax tRAS and tRFC to about 38 and 420... Then give memtest another shot...
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post #4338 of 4441
Quote:
Originally Posted by ducegt View Post

Set Twr and Tfaw to 24 and see if you can get that stable first. You can then work on lowering them after if your anal about it.

Thanks for suggestion. I will try it smile.gif
post #4339 of 4441
Quote:
Originally Posted by Enterprise24 View Post

Can anyone tell me that this is memory instability or cache relate ? 1 error at 330% Thanks in advance.

VCORE 1.365V set 1.344V actual
VCCIO 1.225V set 1.248V actual
VCCSA 1.275V set 1.296V actual
VDIMM 1.45V set 1.48V actual
Warning: Spoiler! (Click to show)

tRAS is too low. tRAS=CAS+tRCD+tRRP (+/-2) so 28 is too low and this causes the value to be set aribtrarly during POST to correct the timing error - and the corrected value is not shown by any OS software. The RAS window needs to be open long enough for all three operations to take place. You also have trp and faw (faw = 4x tRDD) set too low for cas being that high. ANd because of this the RTLs and IOLs are not aligned properly.

did you set those secondaries manually?
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post #4340 of 4441
Quote:
Originally Posted by Jpmboy View Post

tRAS is too low. tRAS=CAS+tRCD+tRRP (+/-2) so 28 is too low and this causes the value to be set aribtrarly during POST to correct the timing error - and the corrected value is not shown by any OS software. The RAS window needs to be open long enough for all three operations to take place. You also have trp and faw (faw = 4x tRDD) set too low for cas being that high. ANd because of this the RTLs and IOLs are not aligned properly.

did you set those secondaries manually?

Yes I set everything manually primary secondary tertiary / advanced timing. I think advanced timing (bank rank structure) has major impact on stability. If I set them auto sometime after "new" training like changing from default UEFI to 4200Mhz profile will cause memtest to throw error very early. So I lock them after seeing that it survive 300% hci.

But for small error like this I will try relax timing like many people said. Just try upping VDIMM to 1.46V (1.488V in hwinfo64) but get error at 310%. So this is incorrect timing rather than voltage or cache instability right ?
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