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*Official* Intel DDR4 24/7 Memory Stability Thread - Page 65

post #641 of 4906
Thread Starter 
Quote:
Originally Posted by Jpmboy View Post

eh, what ever settings I'm running ATM on z170, x79 and x99 are it until Sunday... Added cpu folding to each client. OPened the windows and let 'em fold (36h in.. 6 days to go) blinksmiley.gif
(told the team I'm good for >2.5M PPD ohno-smiley.gif )

He was asking if it was ok to lower this below the threshold and I didn't realise/read it correctly - not related to your (age problem tongue.gif) mistake yesterday redface.gif


P.S Stop folding biggrin.gif
post #642 of 4906
Quote:
Originally Posted by Silent Scone View Post

He was asking if it was ok to lower this below the threshold and I didn't realise/read it correctly - not related to your (age problem tongue.gif) mistake yesterday redface.gif


P.S Stop folding biggrin.gif

I'm on a folding bender ohno-smiley.gif

One thing being misread is the CAS / TRDWR finding ... it's not "12" unless you are running CAS 12. (that's the main problem with extreme guides leaving the Reservation)

Encountered this while trying to bench Samsung D-die and E-die with tertiary on auto using Maximus VIII Gene and Extreme . The culprit to blame are TRDWR_sg TRDWR_dg and TRDWR_dr + TRDWR_dd . When going higher than 3600 these need to be set on same level as CAS value otherwise board will give you a nice 55 POST CODE to look at.
Edited by Jpmboy - 2/2/16 at 6:22am
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post #643 of 4906
Brilliant. I kind of start to understand it now (within reason tongue.gif). I appreciate the info from you all thanks !!

And yes Silentscone I keep a comprehensive guide to every little thing I change and I also have more than the allotted number of OC profiles !!

Few days off to catch up on some paperwork and some Hearthstone then im going to start tweaking the tertiarys some more !
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post #644 of 4906
Hello

As I have wrote before the easiest way to understand timing relationships is to study timing diagrams. At first the diagrams will make little sense. Research the timing settings of interest to gain an understanding of what their purpose is. Once this is done the diagrams make it easy to visualize the relationships each have to each other. The diagram below illustrates the relationship of tRRD and tFAW. As noted the diagram is time sliced which means more clock cycles are taking place than shown. However, all slices will be set to the same value so the diagram can be viewed as is. Viewing the diagram as is it is easy to see that tRRD is set to 4 clock cycles and tFAW is set to 13 clock cycles. Researching these 2 timing parameters one will find what Raja has wrote above and all should make sense.

This brings to mind something else that is brought up quite often which is why do memory manufacturers program the SPD for some of the timings as they do. If 4 clock cycles is the minimum for tRRD and and tFAW minimum is 4 x tRRD why are these values higher by default? Memory specifications are no different than Intel selling a CPU at a qualified speed. The component is guaranteed to work for its intended purpose at the given specs. tRRD and tFAW values are based on chip page size. Per specs for 2400MHz memory speed with a 2k page size minimum tRRD_S is 4 clock cycles or 5.3ns, whichever is greater. A spacing of 5.3ns is equal to 6.4 clock cycles. To meet specs the memory manufacturer would set tRRD to 7 clock cycles. Likewise tFAW requirements are 28 clocks or 30ns, whichever is greater. 30ns is 36 clock cycles so to meet the requirement of whichever is greater the SPD would be set to 36 clocks instead of 28.


post #645 of 4906
Thank you for the input Praz. Very much appriciated.

Worthwhile reading the documents over on https://www.jedec.org/ as you said before then.

While alot of stuff goes over my head, it will stick if I read it enough tongue.gif
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post #646 of 4906
Quote:
Originally Posted by llantant View Post

Thank you for the input Praz. Very much appriciated.

Worthwhile reading the documents over on https://www.jedec.org/ as you said before then.

While alot of stuff goes over my head, it will stick if I read it enough tongue.gif

reading the JEDEC spec DEFINITELY requires a few pints. smile.gif
As a once practicing medicinal chemist, I can say I was able to find a cure for insomnia in it tho.
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post #647 of 4906
Quote:
Originally Posted by Jpmboy View Post

reading the JEDEC spec DEFINITELY requires a few pints. smile.gif
As a once practicing medicinal chemist, I can say I was able to find a cure for insomnia in it tho.

Haha thumb.gif
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post #648 of 4906
Thread Starter 
Quote:
Originally Posted by llantant View Post

Thank you for the input Praz. Very much appriciated.

Worthwhile reading the documents over on https://www.jedec.org/ as you said before then.

While alot of stuff goes over my head, it will stick if I read it enough tongue.gif


I was having this discussion earlier, although the papers may have some digestible content it's aimed primarily at people who are presumed to have a certain level of understanding. Which out of all the people posting here really only applies to Raja and Praz lol. Although I will say that the Micron papers have some diagrams which are pretty well laid out.

Also the way you have to look at it is why do I need to know this. We are all here because we are at least somewhat passionate about PC's, but that doesn't change the fact that as a subsystem, altering what is being predefined for us already has very little gains. The boards do a great job of this already. The fact there is little understanding there cements that for me personally, beyond the primaries and raw frequency scaling.
Quote:
Originally Posted by Praz View Post

Hello

As I have wrote before the easiest way to understand timing relationships is to study timing diagrams. At first the diagrams will make little sense. Research the timing settings of interest to gain an understanding of what their purpose is. Once this is done the diagrams make it easy to visualize the relationships each have to each other. The diagram below illustrates the relationship of tRRD and tFAW. As noted the diagram is time sliced which means more clock cycles are taking place than shown. However, all slices will be set to the same value so the diagram can be viewed as is. Viewing the diagram as is it is easy to see that tRRD is set to 4 clock cycles and tFAW is set to 13 clock cycles. Researching these 2 timing parameters one will find what Raja has wrote above and all should make sense.

This brings to mind something else that is brought up quite often which is why do memory manufacturers program the SPD for some of the timings as they do. If 4 clock cycles is the minimum for tRRD and and tFAW minimum is 4 x tRRD why are these values higher by default? Memory specifications are no different than Intel selling a CPU at a qualified speed. The component is guaranteed to work for its intended purpose at the given specs. tRRD and tFAW values are based on chip page size. Per specs for 2400MHz memory speed with a 2k page size minimum tRRD_S is 4 clock cycles or 5.3ns, whichever is greater. A spacing of 5.3ns is equal to 6.4 clock cycles. To meet specs the memory manufacturer would set tRRD to 7 clock cycles. Likewise tFAW requirements are 28 clocks or 30ns, whichever is greater. 30ns is 36 clock cycles so to meet the requirement of whichever is greater the SPD would be set to 36 clocks instead of 28.

Warning: Spoiler! (Click to show)
]

Thanks Praz smile.gif +1
Edited by Silent Scone - 2/2/16 at 8:19am
post #649 of 4906
Quote:
Originally Posted by Silent Scone View Post

I was having this discussion earlier, although the papers may have some digestible content it's aimed primarily at people who are presumed to have a certain level of understanding. Which out of all the people posting here really only applies to Raja and Praz lol. Although I will say that the Micron papers have some diagrams which are pretty well laid out.

Also the way you have to look at it is why do I need to know this. We are all here because we are at least somewhat passionate about PC's, but that doesn't change the fact that as a subsystem, altering what is being predefined for us already has very little gains. The boards do a great job of this already. The fact there is little understanding there cements that for me personally, beyond the primaries and raw frequency scaling.

I don't have to know it. I just find it interesting to read about. smile.gif
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post #650 of 4906
Thread Starter 
Quote:
Originally Posted by llantant View Post

I don't have to know it. I just find it interesting to read about. smile.gif

I think it's arguable which is more dangerous as we've established today tongue.gif That's aimed at myself aswell. Especially considering I've now earned my third flame from misinterpreting what you were asking and giving a partial answer
Edited by Silent Scone - 2/2/16 at 8:24am
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