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*Official* Intel DDR4 24/7 Memory Stability Thread - Page 66

post #651 of 5748
Quote:
Originally Posted by Silent Scone View Post

I think it's arguable which is more dangerous as we've established today tongue.gif That's aimed at myself aswell. Especially considering I've now earned my third flame from misinterpreting what you were asking and giving a partial answer

yo dude - congrats on Flame 3 !!
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post #652 of 5748
Quote:
Originally Posted by Silent Scone View Post

I think it's arguable which is more dangerous as we've established today tongue.gif That's aimed at myself aswell. Especially considering I've now earned my third flame from misinterpreting what you were asking and giving a partial answer

cheers.gif

With regards to my own OC tho. Im having some down time, but I was happy with tweaking the secondaries. I have always left them alone but got a nice boost and still kept stability without going over 1.4v.
I'm liking my current setup though, so I think ill let it be for a little while. I just wanted a little bed time reading thumb.gif

More important things to be doing anyway.

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post #653 of 5748
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Quote:
Originally Posted by Jpmboy View Post

yo dude - congrats on Flame 3 !!

I would have preferred it would have been under different circumstances. Such as telling some oink to stop wrecking something on their system - but instead it was among friends. Feels a little empty. sad-smiley-002.gif


Thanks lol
Quote:
Originally Posted by llantant View Post

cheers.gif

With regards to my own OC tho. Im having some down time, but I was happy with tweaking the secondaries. I have always left them alone but got a nice boost and still kept stability without going over 1.4v.
I'm liking my current setup though, so I think ill let it be for a little while. I just wanted a little bed time reading thumb.gif

More important things to be doing anyway.



lol - realisation kicks in that you have a fast machine there smile.gif
Edited by Silent Scone - 2/2/16 at 8:52am
post #654 of 5748
Quote:
Originally Posted by Silent Scone View Post

I would have preferred it would have been under different circumstances. Such as telling some oink to stop wrecking something on their system - but instead it was among friends. Feels a little empty. sad-smiley-002.gif


Thanks lol

Nothing empty about it!!
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post #655 of 5748
Quote:
Originally Posted by Praz View Post

Hello

As I have wrote before the easiest way to understand timing relationships is to study timing diagrams. At first the diagrams will make little sense. Research the timing settings of interest to gain an understanding of what their purpose is. Once this is done the diagrams make it easy to visualize the relationships each have to each other. The diagram below illustrates the relationship of tRRD and tFAW. As noted the diagram is time sliced which means more clock cycles are taking place than shown. However, all slices will be set to the same value so the diagram can be viewed as is. Viewing the diagram as is it is easy to see that tRRD is set to 4 clock cycles and tFAW is set to 13 clock cycles. Researching these 2 timing parameters one will find what Raja has wrote above and all should make sense.

This brings to mind something else that is brought up quite often which is why do memory manufacturers program the SPD for some of the timings as they do. If 4 clock cycles is the minimum for tRRD and and tFAW minimum is 4 x tRRD why are these values higher by default? Memory specifications are no different than Intel selling a CPU at a qualified speed. The component is guaranteed to work for its intended purpose at the given specs. tRRD and tFAW values are based on chip page size. Per specs for 2400MHz memory speed with a 2k page size minimum tRRD_S is 4 clock cycles or 5.3ns, whichever is greater. A spacing of 5.3ns is equal to 6.4 clock cycles. To meet specs the memory manufacturer would set tRRD to 7 clock cycles. Likewise tFAW requirements are 28 clocks or 30ns, whichever is greater. 30ns is 36 clock cycles so to meet the requirement of whichever is greater the SPD would be set to 36 clocks instead of 28.



Can i ask where you get timing diagrams like that for ddr4? Thnx.
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post #656 of 5748
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post #657 of 5748
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Quote:
Originally Posted by michael-ocn View Post

Can i ask where you get timing diagrams like that for ddr4? Thnx.

http://www.anandtech.com/show/3851/everything-you-always-wanted-to-know-about-sdram-memory-but-were-afraid-to-ask

Obviously nothing here on Bank Groups (Which is probably for the better), but this is a great reference point.
post #658 of 5748
Quote:
Originally Posted by michael-ocn View Post

Can i ask where you get timing diagrams like that for ddr4? Thnx.

Hello

That is from a JEDEC doc.
post #659 of 5748
Quote:
Originally Posted by Silent Scone View Post

I would have preferred it would have been under different circumstances. Such as telling some oink to stop wrecking something on their system - but instead it was among friends. Feels a little empty. sad-smiley-002.gif
A bit too deep with regard to flames. tongue.gif
(earned and deserved )
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post #660 of 5748
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Never too deep.
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