Originally Posted by Sin0822
The overshoot and undershoot shouldn't really be detectable unless you have a scope, I doubt you could detect a 70mv overshoot that lasts less than 10us with a DMM or CPuz software,
they don't poll at a fast enough rate (you need a scope that could poll preferably at twice the rate of the voltage change). Overshoot and undershoot are also things that have been around for a long time, and should be lessened by higher quality or better implementations. LLC doesn't necessarily help reduce it either.
Thanks for the info. I think droop hit the consumer mkt with wolfdale, and MB manufacturers responded with incorporation of LLC in the bios design. LLC cannot damped the voltage excursion at all... As far as seeing the excursion, I have no doubt... it's undetectable w/o a 10usec scope and really needs the intel socket tool. And yes, better components we have today have help tame the extent of the voltage excursion and decay (driving the product electrical specifications).
Now, I'm not in this business but:
LLC has zero effect on overshoot - what it does is allow droop to an extent so that the voltage excursion is, or can be within the voltage ceiling set in bios depending on how much we defeat droop via LLC. So for example, you set a bios vcore (on this platform, on x99 it's VCCIN that's subject to TLCIVS) to 1.45V in bios with LLC set to defeat any droop - eg, hold a steady voltage. You run a high current load (like AVX or FMA3) and with a DMM or OS-based tool see that Vcore hold steady thru several load state transitions - good right? Well in that scenario, when the current load changes from low to max the actual voltage peaked at 1.52V or higher since the vcore is ~ 200mV above the qualified level for the V_OVS specification, for microseconds (an eternity at the 20 or 14nm scale). It occurs at the higher current load as it transitions. Net - voltage hit 1.52V - 70mV above the setting in bios while changing peak current - without any knowledge of the user.
So.. let's say you set the bios to 1.52V and allow 70mV droop at max current eg, minimal Load Line Compensation... under that high load condition the vcore droops to 1.45V exactly where the high current load ran in the previous example but, on load (=current) transition the "Load changed-induced transient voltage spike" hits 1.52V. Same as the previous example. Except the user understands the voltage excursion, and why exactly LLC and vdroop are available to us. And an idle voltage of 1.52V is harmless (or it idle at <1V with adaptive
Transient spikes cause degradation, silently over time with no overt "overvolt" happening. If you run a busy machine for long hours... allow some droop on the rail(s) it's designed into. For benchmarking or short term high OCs... anything goes. Outside of running Kelvin temperatures where the behavior of the circuitry actually changes, it's hard to imagine a situation where the required voltage for an OC can only be met by defeating vdroop, the stability of the load voltage we all want to see in CPUZ or with our DMM is kinda irrelevant. The voltage changes we see with dynamic voltage control (eg, the ramp up from idle at 0.8V to load at 1.45V really has no impact on the magnitude of the V_OVS (voltage spike). If you ever had a high current cpu benchmark run great than crash right when the load stopped... load transition undershoot!
lol - enough rambling. Edited by Jpmboy - 11/3/15 at 6:15am