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Skylake Overclocking Guide [With Statistics] - Page 352

post #3511 of 11368
Quote:
Originally Posted by error-id10t View Post

No.. which makes it scary, Sin posted a picture where you can poke and get the volts though in this thread.

Yeah, decided to research it after posting. Seems like the Hero and Ranger don't have them while the Extreme, Impact and Gene do. The latter three also have external CMOS reset buttons and more USB 3.0 ports....Weird, it's like they were designed later on.
post #3512 of 11368
Quote:
Originally Posted by CC268 View Post

What do you guys consider to be a good CPU temp or temp range at idle?
~5c over room temp
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post #3513 of 11368
Quote:
Originally Posted by Sin0822 View Post

The overshoot and undershoot shouldn't really be detectable unless you have a scope, I doubt you could detect a 70mv overshoot that lasts less than 10us with a DMM or CPuz software, they don't poll at a fast enough rate (you need a scope that could poll preferably at twice the rate of the voltage change). Overshoot and undershoot are also things that have been around for a long time, and should be lessened by higher quality or better implementations. LLC doesn't necessarily help reduce it either.
Thanks for the info. I think droop hit the consumer mkt with wolfdale, and MB manufacturers responded with incorporation of LLC in the bios design. LLC cannot damped the voltage excursion at all... As far as seeing the excursion, I have no doubt... it's undetectable w/o a 10usec scope and really needs the intel socket tool. And yes, better components we have today have help tame the extent of the voltage excursion and decay (driving the product electrical specifications).
Now, I'm not in this business but:
LLC has zero effect on overshoot - what it does is allow droop to an extent so that the voltage excursion is, or can be within the voltage ceiling set in bios depending on how much we defeat droop via LLC. So for example, you set a bios vcore (on this platform, on x99 it's VCCIN that's subject to TLCIVS) to 1.45V in bios with LLC set to defeat any droop - eg, hold a steady voltage. You run a high current load (like AVX or FMA3) and with a DMM or OS-based tool see that Vcore hold steady thru several load state transitions - good right? Well in that scenario, when the current load changes from low to max the actual voltage peaked at 1.52V or higher since the vcore is ~ 200mV above the qualified level for the V_OVS specification, for microseconds (an eternity at the 20 or 14nm scale). It occurs at the higher current load as it transitions. Net - voltage hit 1.52V - 70mV above the setting in bios while changing peak current - without any knowledge of the user.
So.. let's say you set the bios to 1.52V and allow 70mV droop at max current eg, minimal Load Line Compensation... under that high load condition the vcore droops to 1.45V exactly where the high current load ran in the previous example but, on load (=current) transition the "Load changed-induced transient voltage spike" hits 1.52V. Same as the previous example. Except the user understands the voltage excursion, and why exactly LLC and vdroop are available to us. And an idle voltage of 1.52V is harmless (or it idle at <1V with adaptive smile.gif )
Transient spikes cause degradation, silently over time with no overt "overvolt" happening. If you run a busy machine for long hours... allow some droop on the rail(s) it's designed into. For benchmarking or short term high OCs... anything goes. Outside of running Kelvin temperatures where the behavior of the circuitry actually changes, it's hard to imagine a situation where the required voltage for an OC can only be met by defeating vdroop, the stability of the load voltage we all want to see in CPUZ or with our DMM is kinda irrelevant. The voltage changes we see with dynamic voltage control (eg, the ramp up from idle at 0.8V to load at 1.45V really has no impact on the magnitude of the V_OVS (voltage spike). If you ever had a high current cpu benchmark run great than crash right when the load stopped... load transition undershoot!
lol - enough rambling. redface.gif
Edited by Jpmboy - 11/3/15 at 6:15am
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post #3514 of 11368
Quote:
Originally Posted by Cyro999 View Post

~5c over room temp

Alright...I'm pretty close to that...more like 6-8 over...but I'm also running my radiator fans really low too
    
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post #3515 of 11368
Quote:
Originally Posted by Sin0822 View Post

The overshoot and undershoot shouldn't really be detectable unless you have a scope, I doubt you could detect a 70mv overshoot that lasts less than 10us with a DMM or CPuz software, they don't poll at a fast enough rate (you need a scope that could poll preferably at twice the rate of the voltage change). Overshoot and undershoot are also things that have been around for a long time, and should be lessened by higher quality or better implementations. LLC doesn't necessarily help reduce it either.

I detect it by crashing when sudden load changes are in play , the system was stable under full load, and in idle, but when i run something that frequently changed the load amount, like a game it crashed.

Edit, but maybe this is just asus's poor implementation of the offset and adaptive mode ?
Edited by Balu0 - 11/1/15 at 3:34pm
post #3516 of 11368
you could see if setting performance plan to high performance changes anything, that way you force a steady frequency and see if you are more stable then when you let the frequency drop, if you are then it could be voltage levels at lower frequencies, but if it does the same thing then maybe the problem is elsewhere
Edited by Sin0822 - 11/1/15 at 5:03pm
    
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post #3517 of 11368
Quote:
Originally Posted by Jpmboy View Post

Thanks for the info. I think droop hit the consumer mkt with wolfdale, and MB manufacturers responded with incorporation of LLC in the bios design. LLC cannot damped the voltage excursion at all... As far as seeing the excursion, I have no doubt... it's undetectable w/o a 10usec scope and really needs the intel socket tool. And yes, better components we have today have help tame the extent of the voltage excursion and decay (driving the product electrical specifications).
Now, I'm not in this business but:
LLC has zero effect on overshoot - what it does is allow droop to an extent so that the voltage excursion is, or can be within the voltage ceiling set in bios depending on how much we defeat droop via LLC. So for example, you set a bios vcore (on this platform, on x99 it's VCCIN that's subject to TLCIVS) to 1.45V in bios with LLC set to defeat any droop - eg, hold a steady voltage. You run a high current load (like AVX or FMA3) and with out DMM or OS-based tool see that Vcore hold steady thru several load state transitions - good right? Well in that scenario, when the current load changes from low to max the actual voltage peaked at 1.52V or higher since the vcore is ~ 200mV above the qualified level for the V_OVS specification, for microseconds (an eternity at the 20 or 14nm scale). It occurs at the higher current load as it transitions. Net - voltage hit 1.52V - 70mV above the setting in bios while changing peak current - without any knowledge of the user.
So.. let's say you set the bios to 1.52V and allow 70mV droop at max current eg, minimal Load Line Compensation... under that high load condition the vcore droops to 1.45V exactly where the high current load ran in the previous example but, on load (=current) transition the "Load changed-induced transient voltage spike" hits 1.52V. Same as the previous example. Except the user understands the voltage excursion, and why exactly LLC and vdroop are available to us. And an idle voltage of 1.52V is harmless (or it idle at <1V with adaptive smile.gif )
Transient spikes cause degradation, silently over time with no overt "overvolt" happening. If you run a busy machine for long hours... allow some droop on the rail(s) it's designed into. For benchmarking or short term high OCs... anything goes. Outside of running Kelvin temperatures where the behavior of the circuitry actually changes, it's hard to imagine a situation where the required voltage for an OC can only be met by defeating vdroop, the stability of the load voltage we all want to see in CPUZ or with our DMM is kinda irrelevant. The voltage changes we see with dynamic voltage control (eg, the ramp up from idle at 0.8V to load at 1.45V really has no impact on the magnitude of the V_OVS (voltage spike). If you ever had a high current cpu benchmark run great than crash right when the load stopped... load transition undershoot!
lol - enough rambling. redface.gif
im not disagreeing with you lol, and Praz's findings are sound, I am just saying it's not that big of an issue considering there are Intel specifications that have to be followed and considering how manufacturers compete to provide cleaner power I wouldn't worry much about it on a nice board, and its nothing something he can control or look out for.
    
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post #3518 of 11368
Quote:
Originally Posted by Sin0822 View Post

im not disagreeing with you lol, and Praz's findings are sound, I am just saying it's not that big of an issue considering there are Intel specifications that have to be followed and considering how manufacturers compete to provide cleaner power I wouldn't worry much about it on a nice board, and its nothing something he can control or look out for.
Never thought there was disagreement. smile.gif
And thanks for being around these threads!
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post #3519 of 11368
Quote:
Originally Posted by Jpmboy View Post

Never thought there was disagreement. smile.gif
And thanks for being around these threads!
no worries lol, no man thanks for responding to the majority of them, I have so much to do these days I don't find much time to read all the threads anymore
    
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post #3520 of 11368
I'm still waiting to purchase my GPU for my rig but I want to start overclocking my 6700k. Will using the iGPU have any effect on the CPU while overclocking? Will it generate more heat or cause any stability issues?
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