If I understand things correctly, this is what I get when talking about the PCH only - the direct CPU to graphics x16 PCIe Gen3 (or 2x x8 in CF/SLI) doesn't factor into discussion, as is common in both:
The FlexIO is only semi flexible.
For Z97 there was 18x PCIe Gen 2 (5Gb/s each) from the PCH. A maximum of 8x PCIe 2.0 lanes, and a maximum of 6x USB3.0 and 6x SATA III, with an obvious trade-off between those items to remove either 2x USB 3.0, 2x SATA III, or 2x PCIe to facilitate the other. There was an awful lot of switching going on, and many things would get disabled if something else as used. A lot of ASMedia chips were used to drive USB ports and SATA, and the bandwidth available wasn't sufficient in my opinion. SATA III is 6Gb/s whereas the available bandwidth was only 5Gb/s...
The HSIO FlexIO is more flexible than before.
For Z170 there is 20x PCIe Gen 3 (8Gb/s each) from the PCH. There are 5x groups of 4x PCIe 3.0 lanes as a maximum of 20x PCIe Gen 3 lanes plus 6x USB 3.0. So, it's entirely possible to loose a few (4) PCIe lanes to make the total USB 3.0 up to the maximum of 10x USB 3.0. Still only 6x SATA III are supported as maximum (but ASMedia controllers can and are used for more). Intel Rapid Storage Technology is only available on 12 of the lanes, for SATA or PCI storage, but a few SATA can be moved to non-IRST capable locations.
All of this "up to" wording basically means that there's a finite number of lanes, and some lanes can be one thing or another, eg can be PCIe or USB 3.0. So, there is a maximum number for each interface that the PCH will actually natively drive, but not all of those maximums for every interface maybe able to be met with the number of PCIe lanes actually available in total. It's always a trade-off, one thing or the other, sometimes one thing will disable the other eg M.2 vs SATA III.
Let's take a look at that Gigabyte Gaming 7 review (I also have the manual open):
PCe lanes in brackets at the end of each line.
1x PCIe x16 @ x4 - shares bandwidth with M2H_32G. PCIEX4 will be disabled when an SSD is installed in M2H_32G. (4)
3x PCIe Gen 3 x1 (3)
3x SATA Express / 6x SATA III (6)
2x SATA III (via ASM1061 1x PCIe Gen 2 > 2x SATA III) (1)
2x M.2 32G (1st disabled PCIEX4) (M2D_32G disables SATA III) (0)
5x USB3.0 (0)
2x RJ45 Gb LAN (2)
Total 16 lanes
4x USB 3.0 (Chipset+Renesas Hub) (0?)
1x Type-C USB 3.1 (2?)
1x USB 3.1 (2?)
The other 4 lanes?
It's a challenge to find all of the lanes, and quite why manufacturers have chosen to do what they have. I would have liked to see more jumpers to allow the user to disable a 2nd LAN in favour of keeping the PCIe lane for something else, like a PCIe slot. I would have liked to see more jumpers to let the user decide what they want disabled to enable what, rather than being stuck with the choices that have been offered. Z97 was very restrictive in comparison, but even so, there's room for improvement.
I think thy made a typo in the talk of M2H/M2D disabling SATA. A x4 SSD in the M2H slot disables ONLY the PCIEX4 (x16 length @ x4) slot, and doesn't do anything to the SATA ports, or SATA Express. The M2D slot does indeed share bandwidth directly with the SATA ports though, and therein is the trade-off.Edit: The following review site confirms that the Renesas USB3.0 hub uses the 6th USB 3.0 lane form the PCH, not a PCIe lane (6 total USB 3.0 from Z170).
Also, the Intel Alpine Ridge USB 3.1 controller uses 4x PCIe lanes, and accounts for the remaining lanes. All lanes accounted for 6 (USB) + 20 (PCIe/SATA/LAN).
Oh and yes, you were part correct in the 4 PCIe lanes thing. DMI 3.0 is still only 32Gb/s or 8T/s and is a 4x link, so it's is infact true that the CPU talking to the PCH is over a 4x PCIe link way, although that's probably over simplified. DMI 2.0 was also a 4x link, but was noticeably slower at 20 Gb/sEdited by BlueSponge - 10/1/15 at 5:09am